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浏览/检索结果: 共9条，第1-9条 帮助 已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择作者升序作者降序题名升序题名降序发表日期升序发表日期降序提交时间升序提交时间降序 An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017 Cui, Xiaole; Cui, Xiaoxin; Ni, Yewen; Miao, Min; Jin Yufeng 收藏  |  浏览/下载：7/0  |  提交时间：2017/12/03 Crosstalk  crosstalk avoidance code (CAC)  Fibonacci number system (FNS)  redundant codeword  redundant number  through silicon via (TSV)  CHIP  DESIGN   Reliability evaluation of high-performance, low-power FinFET standard cells based on mixed RBB/FBB technique 期刊论文 Journal of Semiconductors, 2017 Wang Tian; Cui Xiaoxin; Ni Yewen; Liao Kai; Liao Nan; Yu Dunshan; Cui Xiaole 收藏  |  浏览/下载：2/0  |  提交时间：2017/12/03 reliability  FinFET  standard cell  low power  VLSI   Reliability evaluation of high-performance,low-power FinFET standard cells based on mixed RBB/FBB technique 期刊论文 Journal of Semiconductors, 2017 Tian Wang; Xiaoxin Cui; Yewen Ni; Kai Liao; Nan Liao; Dunshan Yu; Xiaole Cui 收藏  |  浏览/下载：3/0  |  提交时间：2017/12/03 reliability  FinFET  standard cell  low power  VLSI   Reliability evaluation of high-performance, low-power FinFET standard cells based on mixed RBB/FBB technique 期刊论文 半导体学报（英文版）, 2017 Tian Wang; Xiaoxin Cui; Yewen Ni; Kai Liao; Nan Liao; Dunshan Yu; Xiaole Cui 收藏  |  浏览/下载：4/0  |  提交时间：2017/12/03 reliability FinFET standard cell low power VLSI  reliability  FinFET  standard cell  low power  VLSI   A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications 其他 2015-01-01 Liao, Nan; Cui, Xiaoxin; Wang, Tian; Liao, Kai; Ni, Yewen; Yu, Dunshan; Cui, Xiaole 收藏  |  浏览/下载：7/0  |  提交时间：2017/12/03 Employing the mixed FBB/RBB in the design of FinFET logic gates 其他 2015-01-01 Wang, Tian; Cui, Xiaoxin; Liao, Kai; Liao, Nan; Ni, Yewen; Yu, Dunshan; Cui, Xiaole 收藏  |  浏览/下载：4/0  |  提交时间：2017/12/03 A High-efficient and Accurate Fault Model Aiming at FPGA-based AES Cryptographic Applications 其他 2015-01-01 Liao, Nan; Cui, Xiaoxin; Wang, Tian; Liao, Kai; Ni, Yewen; Yu, Dunshan; Cui, Xiaole 收藏  |  浏览/下载：5/0  |  提交时间：2017/12/03 Setup time variation  FPGA  Fault model   Employing the mixed FBB/RBB in the design of FinFET logic gates (CPCI-S收录) 会议 作者:   收藏  |  浏览/下载：1/0  |  提交时间：2019/04/11 Back-Gate Biasing  FinFET  Series Structure  Leakage   A High-efficient and Accurate Fault Model Aiming at FPGA-based AES Cryptographic Applications (CPCI-S收录) 会议 作者:   收藏  |  浏览/下载：0/0  |  提交时间：2019/04/11 Setup time variation  FPGA  Fault model