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	A High-efficient and Accurate Fault Model Aiming at FPGA-based AES Cryptographic Applications
	Liao, Nan ; Cui, Xiaoxin ; Wang, Tian ; Liao, Kai ; Ni, Yewen ; Yu, Dunshan ; Cui, Xiaole
	2015
关键词	Setup time variation FPGA Fault model
英文摘要	Setup time variation fault attacks that aim straightly at the FPGA devices have become hot spots nowadays. A high-efficient and accurate fault model aiming at FPGA-based cryptographic applications is proposed in this paper. Multi-diagonal faults are considered in this paper, thus more exploitable faulty ciphertexts can be gathered compared with the previous model. Multi-fault analysis is introduced due to the existence of multi-fault injection, which guarantees the accuracy of the result. Experiment result shows that the fault model brings a significant increase up to 36.5% of the exploitable faults compared with the previous method. Within 24 pairs of correct and faulty ciphertexts, the complete round key can be retrieved by this model.; National Natural Science Foundation of China [61306040]; Beijing Natural Science Foundation [4152020]; R&D project of Shenzhen Government, China [JCYJ20140417144423194, JCYJ20140417144423198]; CPCI-S(ISTP)
语种	英语
出处	11th IEEE International Conference on ASIC (ASICON)
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/470317]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Liao, Nan,Cui, Xiaoxin,Wang, Tian,et al. A High-efficient and Accurate Fault Model Aiming at FPGA-based AES Cryptographic Applications. 2015-01-01.

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