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	A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications
	Liao, Nan ; Cui, Xiaoxin ; Wang, Tian ; Liao, Kai ; Ni, Yewen ; Yu, Dunshan ; Cui, Xiaole
	2015
英文摘要	Setup time variation fault attacks that aim straightly at the FPGA devices have become hot spots nowadays. A high-efficient and accurate fault model aiming at FPGA-based cryptographic applications is proposed in this paper. Multi-diagonal faults are considered in this paper, thus more exploitable faulty ciphertexts can be gathered compared with the previous model. Multi-fault analysis is introduced due to the existence of multi-fault injection, which guarantees the accuracy of the result. Experiment result shows that the fault model brings a significant increase up to 36.5% of the exploitable faults compared with the previous method. Within 24 pairs of correct and faulty ciphertexts, the complete round key can be retrieved by this model. ? 2015 IEEE.; EI
语种	英语
出处	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
DOI标识	10.1109/ASICON.2015.7517030
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/449290]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Liao, Nan,Cui, Xiaoxin,Wang, Tian,et al. A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications. 2015-01-01.

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