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	Employing the mixed FBB/RBB in the design of FinFET logic gates
	Wang, Tian ; Cui, Xiaoxin ; Liao, Kai ; Liao, Nan ; Ni, Yewen ; Yu, Dunshan ; Cui, Xiaole
	2015
英文摘要	Series structures are inevitable and common in the design of digital logic gates. In this paper, to reduce the leakage power, we transplant the technique of mixed forward and reverse back-gate bias (mixed FBB/RBB) from FinFET forced stacks to the more widely-used series structures in FinFET logic gates. By employing the mixed FBB/RBB technique, the goal of leakage reduction is achieved without speed penalty. Performance of series structures of NMOS/PMOS transistors are studied. Simulation results based on the Predictive Technology Model 32nm FinFET model indicate that the speed can be maintained the same while reducing the leakage up to a factor of 18.3 compared with the structure without mixed back-gate biasing. This approach provides us a new viewpoint in designing low stand-by circuits without any sacrifice in the speed. The 16-bit ripple carry adder based on this methodology can acquire at least 51.8% leakage reduction. ? 2015 IEEE.; EI
语种	英语
出处	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
DOI标识	10.1109/ASICON.2015.7517049
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/449298]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Wang, Tian,Cui, Xiaoxin,Liao, Kai,et al. Employing the mixed FBB/RBB in the design of FinFET logic gates. 2015-01-01.

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