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北京大学 [2]

西安交通大学 [1]

北京航空航天大学 [1]

计算技术研究所 [1]

自动化研究所 [1]

武汉大学 [1]

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	Integrating Two Logics Into One Crossbar Array for Logic Gate Design 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 卷号: 68, 期号: 8, 页码: 2987-2991 作者: Yao, Lian; Liu, Peng; Wu, Jigang; Han, Yinhe; Zhong, Yuehang 收藏 \| 浏览/下载：32/0 \| 提交时间：2021/12/01 Logic gates Memristors Logic arrays Resistance Logic functions Adders Switches Logic gates memristive crossbar material implication not material implication 1-bit full adder
	High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films 期刊论文 ACS NANO, 2017 Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao 收藏 \| 浏览/下载：2/0 \| 提交时间：2017/12/03 carbon nanotube complementary metal-oxide semiconductor field-effect transistors medium-scale integrated circuits network film FIELD-EFFECT TRANSISTORS DOPING-FREE FABRICATION LOGIC-CIRCUITS THRESHOLD VOLTAGE OXIDE ELECTRONICS NETWORKS UNIFORM
	Multi-valued logic design methodology with double negative differential resistance transistors 期刊论文 MICRO & NANO LETTERS, 2017, 卷号: 12, 期号: 10 作者: Ji, Yuchao; Chang, Sheng; Wang, Hao; Huang, Qijun; He, Jin 收藏 \| 浏览/下载：2/0 \| 提交时间：2019/12/05 logic gates negative resistance circuits field effect transistors adders multivalued logic design methodology binary logic logic density circuit structure double negative differential resistance field effect transistor monostable-multistable transition logic element MMLE MVL ternary logic gates ternary four-input full adder function circuits binary circuit ternary circuit information load ability
	An Efficient Racetrack Memory-Based Processing-In-Memory Architecture for Convolutional Neural Networks 会议论文 2017 15TH IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING WITH APPLICATIONS AND 2017 16TH IEEE INTERNATIONAL CONFERENCE ON UBIQUITOUS COMPUTING AND COMMUNICATIONS (ISPA/IUCC 2017), 2017-01-01 作者: Liu, Bicheng; Gu, Shouzhen; Chen, Mingsong; Kang, Wang; Hu, Jingtong 收藏 \| 浏览/下载：3/0 \| 提交时间：2019/12/30 Bandwidth Complex networks Convolution Domain walls Energy efficiency Magnetic storage Network architecture Neural networks Ubiquitous computing Computing techniques Convolutional neural network Full adders Memory bandwidths Memory wall Processing in memory Skyrmion State of the art Memory architecture
	Simplified carry save adder-based array multiplier scheme and circuits design 期刊论文 INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2015 Jia, Song; Lyu, Shigong; Li, Xiayu; Liu, Li; He, Yandong 收藏 \| 浏览/下载：2/0 \| 提交时间：2017/12/03 array multiplier carry save adders partial products high speed low power PERFORMANCE LOW-POWER CMOS
	Concurrent error detection adder based on two paths output computation 会议论文作者: Khedhiri, Chiraz; Karmani, Mouna; Hamdi, Belgacem; Man, Ka Lok 收藏 \| 浏览/下载：2/0 \| 提交时间：2019/12/10 Concurrent error detection Dual modular redundancy Full adders Standard CMOS Style designs Transient faults Transistor count Two paths
	高性能浮点DSP中ALU的研究与设计学位论文工学硕士, 中国科学院自动化研究所: 中国科学院研究生院, 2005 王桐收藏 \| 浏览/下载：80/0 \| 提交时间：2015/09/02 浮点ALU 双路径并行前导 1 预测并行舍入复合加法器 Floating-Point ALU Double Datapath Leading-One Prediction Parallel Rounding Compound Adder

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