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	An Efficient Racetrack Memory-Based Processing-In-Memory Architecture for Convolutional Neural Networks
	Liu, Bicheng; Gu, Shouzhen; Chen, Mingsong; Kang, Wang; Hu, Jingtong; Zhuge, Qingfeng; Sha, Edwin H-M
	2017
会议名称	2017 15TH IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING WITH APPLICATIONS AND 2017 16TH IEEE INTERNATIONAL CONFERENCE ON UBIQUITOUS COMPUTING AND COMMUNICATIONS (ISPA/IUCC 2017)
会议日期	2017-01-01
关键词	Bandwidth Complex networks Convolution Domain walls Energy efficiency Magnetic storage Network architecture Neural networks Ubiquitous computing Computing techniques Convolutional neural network Full adders Memory bandwidths Memory wall Processing in memory Skyrmion State of the art Memory architecture
页码	383-390
收录类别	CPCI-S
URL标识	查看原文
WOS记录号	WOS:000464435000051
内容类型	会议论文
URI标识	http://www.corc.org.cn/handle/1471x/5943615
专题	北京航空航天大学
推荐引用方式 GB/T 7714	Liu, Bicheng,Gu, Shouzhen,Chen, Mingsong,et al. An Efficient Racetrack Memory-Based Processing-In-Memory Architecture for Convolutional Neural Networks[C]. 见:2017 15TH IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING WITH APPLICATIONS AND 2017 16TH IEEE INTERNATIONAL CONFERENCE ON UBIQUITOUS COMPUTING AND COMMUNICATIONS (ISPA/IUCC 2017). 2017-01-01.

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