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浏览/检索结果: 共6条，第1-6条 帮助 已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择发表日期升序发表日期降序作者升序作者降序提交时间升序提交时间降序题名升序题名降序 A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for if sampling 期刊论文 Journal of Semiconductors, 2013, 卷号: 34, 期号: [db:dc_citation_issue] 作者:  Chen, Zhenhai;  Qian, Hongwen;  Huang, Songren;  Zhang, Hong;  Yu, Zongguang 收藏  |  浏览/下载：6/0  |  提交时间：2019/12/10 charge domain  Delay-locked loops  Low Power  Pipelined analog-to-digital converter  Sampling switches  Time-interleaved   Influence of phase truncation noise on GPS digital delay-locked loop (DLL) tracking performance 期刊论文 2010, 2010 Li Chan; Cui Xiaowei; Li Guoming; Lu Mingquan; Feng Zhenming 收藏  |  浏览/下载：3/0 Design of a delay locked loop for frequency synthesizer 期刊论文 2010, 2010 Shangguan Li-qing; Liu Bo-an 收藏  |  浏览/下载：14/0 Automatic IQ phase calibration design in a 2.4 GHz direct conversion receiver 期刊论文 2010, 2010 Liu Ruifeng; Li Yongming; Chen Hongyi; Wang Zhihua 收藏  |  浏览/下载：5/0 Analysis and simulation of the tracking performance of different intermediate frequency sampling rate 期刊论文 2010, 2010 Li Chan; Cui Xiaowei; Lu Mingquan; Feng Zhenming 收藏  |  浏览/下载：3/0 A Fast-lock Digital Delay-Locked Loop Controller 会议论文 作者:  Ye, Bo;  Li, Tianwang;  Han, Xingcheng;  Luo, Min 收藏  |  浏览/下载：3/0  |  提交时间：2019/12/05 Delay-locked loops (DLL)  delay compensation circuit (DCC)  PVT