QQ客服 官方微博 反馈留言

	Design of a delay locked loop for frequency synthesizer
	Shangguan Li-qing ; Liu Bo-an
	2010-05-07 ; 2010-05-07
关键词	Practical/ delay lock loops frequency synthesizers oscillators/ delay locked loop frequency synthesizer oscillator programmable multiplication ratio PLL delay-locked loop programmable clock multiplication phase detector CMOS technology power dissipation 1.56 to 100 MHz 0.18 micron 1.8 V/ B1230B Oscillators B1265Z Other digital circuits B1265A Digital circuit design, modelling and testing/ frequency 1.56E+06 to 1.0E+08 Hz size 1.8E-07 m voltage 1.8E+00 V
中文摘要	A delay locked loop (DLL) for frequency synthesizer is designed. By using a conditional oscillator, the DLL achieves programmable multiplication ratio like PLL, while maintaining advantages of conventional DLL as single-pole system and low jitter. By setting initial delay of the delay cell and adopting a new type of phase detector, it can operate over a wide range, thus satisfying the demand of a frequency synthesizer. The DLL, implemented in SMIC's 0.18 mu m 1.8 V CMOS technology, can operate from 1.56 MHz to 100 MHz, and has a frequency range from 20 MHz to 100 MHz with optional multiplication ratios from 1 to 16. At minimum input frequency and maximum multiplication ratio, the synthesizer has a power dissipation of about 9 mW and a jitter of about 92 ps.
语种	中文 ; 中文
出版者	Editorial Dept. Microelectronics ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/16681]
专题	清华大学
推荐引用方式 GB/T 7714	Shangguan Li-qing,Liu Bo-an. Design of a delay locked loop for frequency synthesizer[J],2010, 2010.
APA	Shangguan Li-qing,&Liu Bo-an.(2010).Design of a delay locked loop for frequency synthesizer..
MLA	Shangguan Li-qing,et al."Design of a delay locked loop for frequency synthesizer".(2010).

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。