中国开放科研知识云: 检索

验证码:

换一张

忘记密码？记住我

取消登录

CORC

首页
科研机构
检索
知识图谱
申请加入
托管服务

在结果中检索

科研机构

清华大学 [14]

半导体研究所 [7]

北京大学 [5]

西安交通大学 [4]

兰州理工大学 [1]

大连理工大学 [1]

内容类型

期刊论文 [31]

会议论文 [6]

发表日期

学科主题

光电子学 [2]

半导体材料 [2]

943.3 Spec... [1]

空间技术 [1]

知识图谱

CORC

已提交作品

待认领作品

已认领作品

未提交全文

浏览/检索结果: 共39条，第1-10条

帮助

已选(0)清除条数/页：排序方式：
	Unified forms of the CDR method of approximate reasoning on Antanassov's intuitionistic fuzzy sets and its property analysis 期刊论文 Computational Intelligence, 2018, 卷号: 34, 期号: 4, 页码: 1101-1121 作者: Li, Jun; Xu, Xiaofu 收藏 \| 浏览/下载：2/0 \| 提交时间：2020/11/14 Clock and data recovery circuits (CDR circuits) Fuzzy sets Robustness (control systems) consequent dilation rule (CDR) continuity Implication operators Intuitionistic fuzzy reasonings Reductivity
	Using cell phone location to assess misclassification errors in air pollution exposure estimation (EI收录) 期刊论文 Environmental Pollution, 2018, 卷号: 233, 页码: 261-266 作者: Yu, Haofei[1,2]; Russell, Armistead[1]; Mulholland, James[1]; Huang, Zhijiong[3] 收藏 \| 浏览/下载：115/0 \| 提交时间：2019/04/22 Air pollution Air quality Cellular telephones Clock and data recovery circuits (CDR circuits) Errors Location Pollution Telecommunication equipment Telephone sets
	Energy-Efficient Time Synchronization Based on Asynchronous Source Clock Frequency Recovery and Reverse Two-Way Message Exchanges in Wireless Sensor Networks 会议论文作者: Kim, Kyeong Soo; Lee, Sanghyuk; Lim, Eng Gee 收藏 \| 浏览/下载：5/0 \| 提交时间：2019/11/26 energy efficiency Time synchronization clock frequency recovery wireless source sensor networks two-way message exchanges
	Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process 期刊论文 INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2017 Wang, Yuan; Liu, Yuequan; Jia, Song; Zhang, Xing 收藏 \| 浏览/下载：8/0 \| 提交时间：2017/12/03 delay-locked loop (DLL) clock and data recovery (CDR) jitter operating range PERFORMANCE LINE
	Statistical analysis and quality control for GPS fractional cycle bias and integer recovery clock estimation with raw and combined observation models 期刊论文 ADVANCES IN SPACE RESEARCH, 2017, 卷号: 60, 期号: 12 作者: Cheng, Shuyang; Wang, Jinling; Peng, Wenjie 收藏 \| 浏览/下载：3/0 \| 提交时间：2019/12/05 Precise point positioning Ambiguity resolution Fractional cycle bias Integer recovery clock Quality control
	基于改进光电振荡器结构的超短光帧时钟脉冲提取期刊论文 2016, 2016 解析; 霍力; 王强; 王东; 娄采云; Xie Xi; Huo Li; Wang Qiang; Wang Dong; Lou Caiyun 收藏 \| 浏览/下载：50/0
	A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 2, 页码: 578-586 作者: Chen, Shuai; Li, Hao; Chiang, Patrick Yin 收藏 \| 浏览/下载：22/0 \| 提交时间：2019/12/13 All-digital clock and data recovery (ADCDR) delay-locked loop (DLL) forwarded-clock (FC) receiver high-density interconnect jitter tolerance multicore processor process variation voltage and temperature drift
	A linear phase interpolator for clock and data recovery circuits 期刊论文 Hsi-An Chiao Tung Ta Hsueh/Journal of Xi'an Jiaotong University, 2016, 卷号: 50, 页码: 48-54 作者: Zhang, Yao; Zhang, Hong; Li, Liang; Du, Xin; Cheng, Jun 收藏 \| 浏览/下载：1/0 \| 提交时间：2019/11/26 Clock recovery Common-gate transistor Current sources Inverse functions Linearity Phase interpolation Phase interpolator Tail current source
	A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 2 作者: Chen, Shuai; Li, Hao; Chiang, Patrick Yin 收藏 \| 浏览/下载：5/0 \| 提交时间：2019/12/13 All-digital clock and data recovery (ADCDR) delay-locked loop (DLL) forwarded-clock (FC) receiver high-density interconnect jitter tolerance multicore processor process variation voltage and temperature drift
	180.5Mbps-8Gbps DLL-Based Clock and Data Recovery Circuit with Low Jitter Performance 其他 2015-01-01 Liu, Yuequan; Wang, Yuan; Jia, Song; Zhang, Xing 收藏 \| 浏览/下载：5/0 \| 提交时间：2017/12/03 Clock and data recovery (CDR) wide-range delay-locked loop (DLL) low jitter time-to-digital converter (TDC)

相关链接
欧盟学术资源开放存取平台
CALIS高校机构知识库
台湾学术机构典藏
香港机构知识库整合系统
中国科学院机构知识库网格系统

CORC
关于我们
服务条款
隐私条款

联系我们
0931-8270076
cspace@llas.ac.cn
China-OR

中文简体

©版权所有 ©2017 CSpace - Powered by CSpace