Delay-locked loop based clock and data recovery with wide operating   range and low jitter in a 65-nm CMOS process

doi:10.1002/cta.2267

CORC > 北京大学 > 信息科学技术学院

	Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process
	Wang, Yuan ; Liu, Yuequan ; Jia, Song ; Zhang, Xing
刊名	INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
	2017
关键词	delay-locked loop (DLL) clock and data recovery (CDR) jitter operating range PERFORMANCE LINE
DOI	10.1002/cta.2267
英文摘要	A delay-locked loop (DLL) based clock and data recovery (CDR) circuit with a half-rate clock is proposed. The CDR includes a coarse and a fine tuned block, in which the novel coarse and fine phase detectors form closed loops. It is designed in a 65-nm complementary metal-oxide semiconductor (CMOS) process using a 1.2-V supply voltage. The simulation results show that it can cover a wide operating range from 500Mbps to 8Gbps and the corresponding peak-to-peak jitters are 1.63ps and 0.96ps, respectively. Copyright (c) 2016 John Wiley & Sons, Ltd.; National High Technology Research and Development Program of China [2015AA016601]; SCI(E); ARTICLE; 6; 851-858; 45
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/473074]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Wang, Yuan,Liu, Yuequan,Jia, Song,et al. Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process[J]. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS,2017.
APA	Wang, Yuan,Liu, Yuequan,Jia, Song,&Zhang, Xing.(2017).Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process.INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS.
MLA	Wang, Yuan,et al."Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process".INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS (2017).