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浏览/检索结果: 共5条，第1-5条 帮助 已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择作者升序作者降序题名升序题名降序发表日期升序发表日期降序提交时间升序提交时间降序 Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness 期刊论文 IEICE TRANSACTIONS ON ELECTRONICS, 2017 Wang, Yuan; Lu, Guangyi; Wang, Yize; Zhang, Xing 收藏  |  浏览/下载：3/0  |  提交时间：2017/12/03 electrostatic discharge (ESD)  robustness  false-triggering immunity  transmission-line-pulsing (TLP) test  NANOSCALE CMOS TECHNOLOGY  PROTECTION  DESIGN  NMOS   Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process 期刊论文 IEICE TRANSACTIONS ON ELECTRONICS, 2016 Lu, Guangyi; Wang, Yuan; Zhang, Xing 收藏  |  浏览/下载：5/0  |  提交时间：2017/12/03 electrostatic discharge (ESD)  gate-grounded NMOS (ggNMOS)  substrate-pickup stripes  transmission-line-pulsing (TLP) test  DEVICES  PICKUP  TRANSISTORS  TECHNOLOGY  ROBUSTNESS  IMPACT   Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling 期刊论文 science china information sciences, 2015 Lu, Guang Yi; Wang, Yuan; Zhang, Li Zhong; Cao, Jian; Jia, Song; Zhang, Xing 收藏  |  浏览/下载：3/0  |  提交时间：2015/11/10 A novel multi-finger layout strategy for GGnMOS ESD protection device 其他 2011-01-01 Zhang, Peng; Wang, Yuan; Jia, Song; Zhang, Xing 收藏  |  浏览/下载：4/0  |  提交时间：2015/11/10 A robust novel technique for SPICE simulation of ESD snap-back characteristics 期刊论文 2010, 2010 Jiao Chao; Yu Zhiping 收藏  |  浏览/下载：4/0