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Integrating Two Logics Into One Crossbar Array for Logic Gate Design
期刊论文
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 卷号: 68, 期号: 8, 页码: 2987-2991
作者:
Yao, Lian
;
Liu, Peng
;
Wu, Jigang
;
Han, Yinhe
;
Zhong, Yuehang
收藏
  |  
浏览/下载:32/0
  |  
提交时间:2021/12/01
Logic gates
Memristors
Logic arrays
Resistance
Logic functions
Adders
Switches
Logic gates
memristive crossbar
material implication
not material implication
1-bit full adder
Stretchable and Twistable Resistive Switching Memory with Information Storage and Computing Functionalities
期刊论文
ADVANCED MATERIALS TECHNOLOGIES, 2020
作者:
Lu, Ying
;
Gao, Shuang
;
Li, Fali
;
Zhou, Youlin
;
Xie, Zhuolin
收藏
  |  
浏览/下载:12/0
  |  
提交时间:2020/12/16
ELECTRONICS
SKIN
Implementing digital computing with DNA-based switching circuits
期刊论文
NATURE COMMUNICATIONS, 2020, 卷号: 11, 期号: 1, 页码: -
作者:
Wang, F
;
Lv, H
;
Li, Q
;
Li, J
;
Zhang, XL
收藏
  |  
浏览/下载:23/0
  |  
提交时间:2021/09/06
STRAND-DISPLACEMENT
COMPUTATION
GATE
An STT-MRAM Based in Memory Architecture for Low Power Integral Computing
期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2019, 卷号: 68, 页码: 617-623
作者:
Zhao, Yinglin
;
Ouyang, Peng
;
Kang, Wang
;
Yin, Shouyi
;
Zhang, Youguang
收藏
  |  
浏览/下载:10/0
  |  
提交时间:2019/12/30
Integral histogram
parallel architecture
STT-MRAM
processing in memory
full adder
Multi-valued logic design methodology with double negative differential resistance transistors
期刊论文
MICRO & NANO LETTERS, 2017, 卷号: 12, 期号: 10
作者:
Ji, Yuchao
;
Chang, Sheng
;
Wang, Hao
;
Huang, Qijun
;
He, Jin
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  |  
浏览/下载:2/0
  |  
提交时间:2019/12/05
logic gates
negative resistance circuits
field effect transistors
adders
multivalued logic design methodology
binary logic
logic density
circuit structure
double negative differential resistance field effect transistor
monostable-multistable transition logic element
MMLE
MVL
ternary logic gates
ternary four-input full adder
function circuits
binary circuit
ternary circuit
information load ability
Approximate Computing in MOS/Spintronic Non-Volatile Full-Adder
会议论文
Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2016-01-01
作者:
Cai, Hao
;
Wang, You
;
Naviner, Lirida A. B.
;
Wang, Zhaohao
;
Zhao, Weisheng
收藏
  |  
浏览/下载:14/0
  |  
提交时间:2019/12/30
Approximate computing
UTBB-FDSOI
magnetic tunnel junction
nonvolatile full adder
ultra low power
A signal degradation reduction method for memristor ratioed logic (MRL) gates
期刊论文
IEICE ELECTRONICS EXPRESS, 2015, 卷号: 12, 期号: 8, 页码: 6
作者:
Liu, Bosheng l
;
Wang, Ying
;
You, Zhiqiang
;
Han, Yinhe
;
Li, Xiaowei
收藏
  |  
浏览/下载:15/0
  |  
提交时间:2019/12/13
full adder
memristor ratioed logic (MRL) gate
Simplified carry save adder-based array multiplier scheme and circuits design
期刊论文
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2015
Jia, Song
;
Lyu, Shigong
;
Li, Xiayu
;
Liu, Li
;
He, Yandong
收藏
  |  
浏览/下载:2/0
  |  
提交时间:2017/12/03
array multiplier
carry save adders
partial products
high speed
low power
PERFORMANCE LOW-POWER
CMOS
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction
期刊论文
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 卷号: 62, 页码: 1757-1765
作者:
Deng, Erya
;
Zhang, Yue
;
Kang, Wang
;
Dieny, Bernard
;
Klein, Jacques-Olivier
收藏
  |  
浏览/下载:4/0
  |  
提交时间:2020/01/06
3-D integration
8-bit flip-flop
8-bit full-adder
full non-volatility
STT-MTJ
synchronous
High-Frequency Low-Power Magnetic Full-Adder Based on Magnetic Tunnel Junction With Spin-Hall Assistance
会议论文
IEEE International Magnetics Conference (Intermag), Beijing, PEOPLES R CHINA, 2015-11-01
作者:
Deng, Erya
;
Wang, Zhaohao
;
Klein, Jacques-Olivier
;
Prenat, Guillaume
;
Dieny, Bernard
收藏
  |  
浏览/下载:5/0
  |  
提交时间:2020/01/06
Hybrid logic-in-memory
magnetic full-adder (MFA)
magnetic tunnel junction (MTJ)
spin-Hall effect (SHE)
spin-transfer torque (STT)
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