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浏览/检索结果: 共6条，第1-6条 帮助 限定条件 专题：北京大学    第一署名单位    第一作者单位    通讯作者单位     已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择作者升序作者降序题名升序题名降序发表日期升序发表日期降序提交时间升序提交时间降序 Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2017 Kang, Wang; Chang, Liang; Wang, Zhaohao; Lv, Weifeng; Sun, Guanyu; Zhao, Weisheng 收藏  |  浏览/下载：4/0  |  提交时间：2017/12/03 Asymmetric sensing  dynamic write power  read reliability  STT-MRAM  MEMORY  CIRCUIT  BENCHMARKING  PERFORMANCE  TECHNOLOGY  DEVICES  STORAGE  DESIGN  CACHES  ENERGY   PDS: Pseudo-Differential Sensing Scheme for STT-MRAM 其他 2016-01-01 Kang, Wang; Pang, Tingting; Wu, Bi; Lv, Weifeng; Zhang, Youguang; Sung, Guanyu; Zhao, Weisheng 收藏  |  浏览/下载：1/0  |  提交时间：2017/12/03 STT-MRAM  Asymmetric sensing  Reliability  Write power  Error detection and correction  CIRCUIT  MEMORY  TECHNOLOGY  ENERGY  MODEL   Accelerated Aging in Analog and Digital Circuits With Feedback 期刊论文 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2015 Sutaria, Ketul B.; Mohanty, Abinash; Wang, Runsheng; Huang, Ru; Cao, Yu 收藏  |  浏览/下载：2/0  |  提交时间：2017/12/03 Circuit aging  bias runaway  BTI  CHC  DVS  aging models and simulation framework  BIAS TEMPERATURE INSTABILITY  HOT-CARRIER DEGRADATION  DEEP-SUBMICRON NMOSFETS  E-E SCATTERING  NBTI  RELIABILITY  SIMULATION  DESIGN  CROSS  MODEL   Impact of Temporal Transistor Variations on Circuit Reliability 其他 2015-01-01 Wang, Runsheng; Cao, Yu 收藏  |  浏览/下载：3/0  |  提交时间：2017/12/03 circuit reliability  temporal variation  bias temperature instability (BTI)  random telegraph noise (RTN)   Negative-Bias Temperature Instability in Gate-All-Around Silicon Nanowire MOSFETs: Characteristic Modeling and the Impact on Circuit Aging 期刊论文 ieee电子器件汇刊, 2010 Liu, Changze; Yu, Tao; Wang, Runsheng; Zhang, Liangliang; Huang, Ru; Kim, Dong-Won; Park, Donggun; Wang, Yangyuan 收藏  |  浏览/下载：6/0  |  提交时间：2015/11/10 Circuit aging  negative-bias temperature instability (NBTI) modeling  process variations  silicon nanowire MOSFET (SNWT)  NBTI DEGRADATION  MOS DEVICES  TRANSISTORS  INTERFACE  RELIABILITY  TRANSPORT  DYNAMICS  CARRIER   A Unified FinFET Reliability Model Including High K Gate Stack Dynamic Threshold Voltage, Hot Carrier Injection, and Negative Bias Temperature Instability 其他 2009-01-01 Ma, Chenyue; Li, Bo; Zhang, Lining; He, Jin; Zhang, Xing; Lin, Xinnan; Chan, Mansun 收藏  |  浏览/下载：3/0  |  提交时间：2015/11/12 Model  Reliability  HKSDT  HCI  NBTI  circuit  NBTI DEGRADATION  GENERATION  ELECTRONS