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浏览/检索结果: 共7条，第1-7条 帮助 已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择发表日期升序发表日期降序作者升序作者降序提交时间升序提交时间降序题名升序题名降序 Short channel monolayer MoS2 field-effect transistors defined by SiOx nanofins down to 20nm 期刊论文 NANOTECHNOLOGY, 2019, 卷号: Vol.30 No.29 作者:  Bi, KX;  Liu, HZ;  Chen, YQ;  Luo, F;  Shu, ZW 收藏  |  浏览/下载：3/0  |  提交时间：2019/12/17 short channel devices  hydrogen silsesquioxane (HSQ) electron resists  large area preparation   Short channel monolayer MoS2 field-effect transistors defined by SiOx nanofins down to 20nm 期刊论文 NANOTECHNOLOGY, 2019, 卷号: Vol.30 No.29 作者:  Bi, KX;  Liu, HZ;  Chen, YQ;  Luo, F;  Shu, ZW 收藏  |  浏览/下载：13/0  |  提交时间：2019/12/17 short channel devices  hydrogen silsesquioxane (HSQ) electron resists  large area preparation   Threshold Voltage Characteristics for Silicon Nanowire Field-Effect Transistor With a Double-Layer Gate Structure 期刊论文 IEEE Transactions on Electron Devices, 2019, 卷号: Vol.66 No.1, 页码: 771-776 作者:  Hongguan Yang 收藏  |  浏览/下载：11/0  |  提交时间：2019/12/13 Logic  gates  Threshold  voltage  Silicon  MOSFET  Transconductance  Nanoscale  devices  Double-layer  gate  structure  MOS  devices  short-channel  effect  silicon  nanowire  (Si-NW)  threshold  voltage  characteristics   Threshold Voltage Characteristics for Silicon Nanowire Field-Effect Transistor With a Double-Layer Gate Structure 期刊论文 IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 卷号: Vol.66 No.1, 页码: 771-776 作者:  Yang, HG 收藏  |  浏览/下载：11/0  |  提交时间：2019/12/17 Double-layer gate structure  MOS devices  short-channel effect  silicon nanowire (Si-NW)  threshold voltage characteristics   Characterization of Self-heating Leads to Universal Scaling of HCI Degradation of Multi-Fin SOI FinFETs 其他 2016-01-01 Jiang, Hai; Shin, SangHoon; Liu, Xiaoyan; Zhang, Xing; Alam, Muhammad Ashraful 收藏  |  浏览/下载：6/0  |  提交时间：2017/12/03 Self-heating  Hot carrier injection  Thermal circuit model  universal degradation  Gate-all-around transistors  HOT-CARRIER DEGRADATION  SHORT-CHANNEL TRANSISTORS  TRANSPORT  MOSFETS  DEVICES  NBTI   Gate Underlap Design for Short Channel Effects Control in Cylindrical Gate-all-around MOSFETs based on an Analytical Model 期刊论文 iete technical review, 2012 Zhang, Lining; Wang, Shaodi; Ma, Chenyue; He, Jin; Xu, Chunkai; Ma, Yutao; Ye, Yun; Liang, Hailang; Chen, Qin; Chan, Mansun 收藏  |  浏览/下载：3/0  |  提交时间：2015/11/13 Conformal mapping  Gate-all-around MOSFET  Gate underlap  Short channel effects  TCAD simulations  SOI MOSFETS  FRINGING FIELDS  SCALING THEORY  DEVICES   Quasi-SOI MOSFETs - A promising bulk device candidate for extremely scaled era 期刊论文 ieee电子器件汇刊, 2007 Tian, Yu; Xiao, Han; Huang, Ru; Feng, Chuguang; Chan, Mansun; Chen, Baoqin; Wang, Runsheng; Zhang, Xing; Wang, Yangyuan 收藏  |  浏览/下载：3/0  |  提交时间：2015/11/12 CMOS  drain-induced barrier lowering (DIBL)  quasi-SOI  scaling  short-channel effects (SCEs)  SOI  ultrathin  body (UTB)  CMOS DEVICES