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浏览/检索结果: 共5条，第1-5条 帮助 已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择发表日期升序发表日期降序作者升序作者降序提交时间升序提交时间降序题名升序题名降序 铁电存储器在实时处理系统中的应用 期刊论文 2010, 2010 李迎春; 孙新亚; 朱善君; LI Ying-chun; SUN Xin-ya; Zhu Shang-jun 收藏  |  浏览/下载：2/0 基于FPGA的异步FIFO设计与实现 期刊论文 2010, 2010 熊红兵; 陈琦; Xiong Hongbing; Chen Qi 收藏  |  浏览/下载：1/0 基于双DSP数字化控制的交直流脉冲弧焊逆变电源 期刊论文 2010, 2010 符策健; 朱志明; 纪圣儒; 周雪珍; FU Ce-jian; ZHU Zhi-ming; JI Shen-ru 收藏  |  浏览/下载：3/0 Storage and compression design of high speed CCD (EI CONFERENCE) 会议论文 4th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optical Test and Measurement Technology and Equipment, November 19, 2008 - November 21, 2008, Chengdu, China Cai X.; Zhai L. P. 收藏  |  浏览/下载：47/0  |  提交时间：2013/03/25 In current field of CCD measurement  large area and high resolution CCD is used to obtain big measurement image  so that  speed and capacity of CCD requires high performance of later storage and process system. The paper discusses how to use SCSI hard disk to construct storage system and use DSPs and FPGA to realize image compression. As for storage subsystem  Because CCD is divided into multiplex output  SCSI array is used in RAID0 way. The storage system is composed of high speed buffer  DMA controller  control MCU  SCSI protocol controller and SCSI hard disk. As for compression subsystem  according to requirement of communication and monitor system  the output is fixed resolution image and analog PAL signal. The compression means is JPEG2000 standard  in which  9/7 wavelets in lifting format is used. 2 DSPs and FPGA are used to compose parallel compression system. The system is composed of FPGA pre-processing module  DSP compression module  video decoder module  data buffer module and communication module. Firstly  discrete wavelet transform and quantization is realized in FPGA. Secondly  entropy coding and stream adaption is realized in DSPs. Last  analog PAL signal is output by Video decoder. Data buffer is realized in synchronous dual-port RAM and state of subsystem is transfer to controller. Through subjective and objective evaluation  the storage and compression system satisfies the requirement of system. 2009 SPIE.   Design of test circuit platform for turbo encoder 会议论文 Proceedings of the First International Symposium on Test Automation & Instrumentation, Vols 1 - 3 作者:  Li Ming[1];  Chen Shaokuan[2];  Xiong Qingqing[3];  Liang Weibing[4] 收藏  |  浏览/下载：4/0  |  提交时间：2019/05/10 test circuit  turbo encoder  SCM (single-chip microcomputer)  DPR (dual-port RAM)