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An introduction to CPU and DSP design in China
期刊论文
SCIENCE CHINA-INFORMATION SCIENCES, 2016, 卷号: 59, 期号: 1, 页码: 8
作者:
Hu, Weiwu
;
Zhang, Yifu
;
Fu, Jie
收藏
  |  
浏览/下载:16/0
  |  
提交时间:2019/12/13
Chinese domestic CPUs and DSPs
Loongson CPU
ShenWei CPU
YHFT DSP
BWDSP
Data-Driven H infinity Control for Nonlinear Distributed Parameter Systems
期刊论文
IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS, 2015, 卷号: 26, 页码: 2949-2961
作者:
Luo, Biao
;
Huang, Tingwen
;
Wu, Huai-Ning
;
Yang, Xiong
收藏
  |  
浏览/下载:5/0
  |  
提交时间:2020/01/06
Data driven
distributed parameter systems (DSPs)
Hamilton-Jacobi-Isaacs (HJI) equation
H infinity control
neural network (NN)
off-policy learning
partial differential equation (PDE)
Using paralleled-PEs method to resolve the bursting data in distributed stream processing system
会议论文
IEEE 16th International Conference on Computational Science and Engineering (CSE), Sydney, AUSTRALIA, 2013-01-01
作者:
Zhou, Baojian
;
Luan, Zhongzhi
;
Wu, JieQian
;
Xie, Ming
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  |  
浏览/下载:3/0
  |  
提交时间:2020/01/06
DSPS
DSPA
PE
Hot-Spot
Real-Time
QoS
Designing and development of multi-DSP real-time image processing system based on FPGA (EI CONFERENCE)
会议论文
2011 International Conference on Computer Science and Network Technology, ICCSNT 2011, December 24, 2011 - December 26, 2011, Harbin, China
Wei H.
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  |  
浏览/下载:18/0
  |  
提交时间:2013/03/25
To improve the image processing system of resolution capability and reliability
image processing system in a growing number of multi-sensor model. In this mode
the use of the current main stream single DSP + FPGA hardware architecture for image processing algorithms have already unable to meet the operational requirements of real-time. This paper proposed a new hardware architecture that is the three DSPs based on FPGA. With the traditional master-slave architectures is different
three DSP's external interfaces are connected with FPGA and other peripheral interfaces are connected to the FPGA. In the architecture
DSP is in the same position three and FPGA flow control for data management and other function to achieve. This connection has a strong restructuring and expansion
software development and more flexible. 2011 IEEE.
Design of an INS aided high dynamic GPS Receiver
会议论文
2011 INTERNATIONAL CONFERENCE ON ELECTRONICS, COMMUNICATIONS AND CONTROL (ICECC), 2011-01-01
作者:
Ma Xiaoyong
;
Liu Baiqi
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  |  
浏览/下载:1/0
  |  
提交时间:2020/01/06
GPS receiver
INS aided
DSPs
front-end
基于双DSPs架构的移动机器人运动控制系统的设计
期刊论文
《制造业自动化》, 2010, 页码: 8-11
作者:
李怀俊[1,2]
收藏
  |  
浏览/下载:2/0
  |  
提交时间:2019/04/26
双DSPs架构
控制系统 正交编码脉冲
脉宽调制
Storage and compression design of high speed CCD (EI CONFERENCE)
会议论文
4th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optical Test and Measurement Technology and Equipment, November 19, 2008 - November 21, 2008, Chengdu, China
Cai X.
;
Zhai L. P.
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  |  
浏览/下载:47/0
  |  
提交时间:2013/03/25
In current field of CCD measurement
large area and high resolution CCD is used to obtain big measurement image
so that
speed and capacity of CCD requires high performance of later storage and process system. The paper discusses how to use SCSI hard disk to construct storage system and use DSPs and FPGA to realize image compression. As for storage subsystem
Because CCD is divided into multiplex output
SCSI array is used in RAID0 way. The storage system is composed of high speed buffer
DMA controller
control MCU
SCSI protocol controller and SCSI hard disk. As for compression subsystem
according to requirement of communication and monitor system
the output is fixed resolution image and analog PAL signal. The compression means is JPEG2000 standard
in which
9/7 wavelets in lifting format is used. 2 DSPs and FPGA are used to compose parallel compression system. The system is composed of FPGA pre-processing module
DSP compression module
video decoder module
data buffer module and communication module. Firstly
discrete wavelet transform and quantization is realized in FPGA. Secondly
entropy coding and stream adaption is realized in DSPs. Last
analog PAL signal is output by Video decoder. Data buffer is realized in synchronous dual-port RAM and state of subsystem is transfer to controller. Through subjective and objective evaluation
the storage and compression system satisfies the requirement of system. 2009 SPIE.
基于嵌入式并行系统的智能视频监控关键技术研究
学位论文
工学博士, 中国科学院自动化研究所: 中国科学院研究生院, 2008
作者:
李功燕
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  |  
浏览/下载:103/0
  |  
提交时间:2015/09/02
智能视频监控
嵌入式并行系统
目标检测
多DSP
多摄像头
任务调度
目标跟踪
Intelligent Video Surveillance
Moving Object Detection
Moving Object Tracking
Multi-DSPs
Multiple Cameras
Task Scheduling
Embedded System
Using real-time embedded system with multiple DSPs in corona detection (EI CONFERENCE)
会议论文
ICO20: Optical Information Processing, August 21, 2005 - August 26, 2005, Changchun, China
Yan F.
;
Wang X.
;
Yu X.
;
Sui Y.-X.
;
Jin C.-S.
;
Yang H.-J.
收藏
  |  
浏览/下载:16/0
  |  
提交时间:2013/03/25
The method how to detect and locate corona real-time by double spectrums image
UV spectrum image and visible spectrum image of the object
was introduced. And the construction of an embedded system on which the double spectrums detection method can be realized was also introduced. CCD cameras' control data and their output image data were processed respectively. Using this kind of system
we can find the corona real-time by a combined image
thus where the electric leakage is can be found quickly. Experiments indicate this method and the embedded system with multiple DSPs suits for corona detection.
Statistics measure on the left ventricle with the cardiac MRI films based on DSPs
会议论文
WCICA 2006: Sixth World Congress on Intelligent Control and Automation, Vols 1-12, Conference Proceedings, 2006-06-21
作者:
Xue, Lei[1]
;
Zhang, Zhe[2]
;
Yan, Zhuangzi[3]
;
Peng, Zhiwei[4]
收藏
  |  
浏览/下载:3/0
  |  
提交时间:2019/05/10
image processing
segment
DSPs
ant-snake
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