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浏览/检索结果: 共3条，第1-3条 帮助 限定条件 专题：长春光学精密机械与物理研究所    第一署名单位    第一作者单位    通讯作者单位     已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择作者升序作者降序题名升序题名降序发表日期升序发表日期降序提交时间升序提交时间降序 Optical transmission system based on 10GBASE-X (EI CONFERENCE) 会议论文 2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China Zhao L.-L.; Wu Z.-Y.; Gao S.-J. 收藏  |  浏览/下载：19/0  |  提交时间：2013/03/25 In order to further enhance the bandwidth of the data communication system in theodolite  The whole design of the PMD is realized by using Xenpak optical module. Its duty is responsible for converting 4-channel parallel 3.125Gbps data stream into a serial 10.3126Gbps data stream  a single channel serial optical transmission system was designed based on the studying of the 10BASE-X Gigabit Ethernet physical layer technology which meets the IEEE standard. The conversion between the 64-bit 156.25MHz TTL signals and the 4 channel 3.125Gbps PCML differential signals is carried out by FPGA  and sending out it in the form of light signals. The experimental results show that data transmission capacity was achieved a 10Gbps in the single-channel optical transmission system. It can conduct short distance transmission. The system delay is about 31lns. The bit error rates no more than 10-12  which satisfies the system demand. 2010 IEEE.   Design of image interpretation and data-processing system based on SOPC (EI CONFERENCE) 会议论文 2010 International Conference on Computer, Mechatronics, Control and Electronic Engineering, CMCE 2010, August 24, 2010 - August 26, 2010, Changchun, China Wang Z.-Q.; Liu Z.-R.; Xie M.-J. 收藏  |  浏览/下载：11/0  |  提交时间：2013/03/25 In order to follow the development of image interpretation and data-processing system in photoelectric measurement equipments  a kind of hardware acceleration system is designed where MIMD distributed multi-processor architecture is used with SOPC technology. System hardware is composed of FPGA  SDRAM  SRAM  FLASH  and PCI bridge chip. Four Nios II embedded processors are integrated in a single FPGA chip  and communicate with each other by sharing memory. Experimental results indicate that the system meets the requirements of data-processing system in photoelectric measurement equipments and possesses practical significance for engineering applications. 2010 IEEE.   Embedded system of image storage based on Fiber Channel (EI CONFERENCE) 会议论文 Quantum Optics, Optical Data Storage, and Advanced Microlithography, November 12, 2007 - November 14, 2007, Beijing, China Chen X.; Su W.; Xing Z.; Wang H. 收藏  |  浏览/下载：17/0  |  提交时间：2013/03/25 In domains of aerospace  aviation  aiming  and optic measure etc.  the embedded system of imaging  processing and recording is absolutely necessary  which has small volume  high processing speed and high resolution. But the embedded storage technology becomes system bottleneck because of developing slowly. It is used to use RAID to promote storage speed  but it is unsuitable for the embedded system because of its big volume. Fiber channel (FC) technology offers a new method to develop the high-speed  portable storage system. In order to make storage subsystem meet the needs of high storage rate  make use of powerful Virtex-4 FPGA and high speed fiber channel  advance a project of embedded system of digital image storage based on Xilinx Fiber Channel Arbitrated Loop LogiCORE. This project utilizes Virtex4 RocketIO MGT transceivers to transmit the data serially  and connects many Fiber Channel hard drivers by using of Arbitrated Loop optionally. It can achieve 400MBps storage rate  breaks through the bottleneck of PCI interface  and has excellences of high-speed  real-time  portable and massive capacity.