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浏览/检索结果: 共7条，第1-7条 帮助 限定条件 发表日期：2010     已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择作者升序作者降序题名升序题名降序发表日期升序发表日期降序提交时间升序提交时间降序 RS-485 bus-based high-speed serial remote data transmissions 期刊论文 2010, 2010 Li Cheng; Wang Peng; Ding Tianhuai; Chen Ken; Geng Lizhong 收藏  |  浏览/下载：5/0 Optical disk data stream storing system based on Nios II with CF card 期刊论文 2010, 2010 Wang Yong-rui; Xiong Jian-ping 收藏  |  浏览/下载：4/0 RS-485 bus-based high-speed data/power transmission method for seismic exploration instruments 期刊论文 2010, 2010 Ding Tianhuai; Li Cheng; Wang Peng; Chen Ken; Geng Lizhong 收藏  |  浏览/下载：6/0 Design and implementation of fuzzy controller for engine idle speed 期刊论文 2010, 2010 Liu Han-hui; Jin Wei-wei; Jin Dong-ming 收藏  |  浏览/下载：2/0 Hardware/software co-verification platform for EOS design 期刊论文 2010, 2010 Wang Peng; Jin Depeng; Zeng Lieguang 收藏  |  浏览/下载：3/0 Optical transmission system based on 10GBASE-X (EI CONFERENCE) 会议论文 2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China Zhao L.-L.; Wu Z.-Y.; Gao S.-J. 收藏  |  浏览/下载：19/0  |  提交时间：2013/03/25 In order to further enhance the bandwidth of the data communication system in theodolite  The whole design of the PMD is realized by using Xenpak optical module. Its duty is responsible for converting 4-channel parallel 3.125Gbps data stream into a serial 10.3126Gbps data stream  a single channel serial optical transmission system was designed based on the studying of the 10BASE-X Gigabit Ethernet physical layer technology which meets the IEEE standard. The conversion between the 64-bit 156.25MHz TTL signals and the 4 channel 3.125Gbps PCML differential signals is carried out by FPGA  and sending out it in the form of light signals. The experimental results show that data transmission capacity was achieved a 10Gbps in the single-channel optical transmission system. It can conduct short distance transmission. The system delay is about 31lns. The bit error rates no more than 10-12  which satisfies the system demand. 2010 IEEE.   Design of image interpretation and data-processing system based on SOPC (EI CONFERENCE) 会议论文 2010 International Conference on Computer, Mechatronics, Control and Electronic Engineering, CMCE 2010, August 24, 2010 - August 26, 2010, Changchun, China Wang Z.-Q.; Liu Z.-R.; Xie M.-J. 收藏  |  浏览/下载：11/0  |  提交时间：2013/03/25 In order to follow the development of image interpretation and data-processing system in photoelectric measurement equipments  a kind of hardware acceleration system is designed where MIMD distributed multi-processor architecture is used with SOPC technology. System hardware is composed of FPGA  SDRAM  SRAM  FLASH  and PCI bridge chip. Four Nios II embedded processors are integrated in a single FPGA chip  and communicate with each other by sharing memory. Experimental results indicate that the system meets the requirements of data-processing system in photoelectric measurement equipments and possesses practical significance for engineering applications. 2010 IEEE.