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浏览/检索结果: 共7条，第1-7条 帮助 限定条件 专题：上海大学    第一署名单位    第一作者单位    通讯作者单位     已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择作者升序作者降序题名升序题名降序发表日期升序发表日期降序提交时间升序提交时间降序 The Yin and Yang of BK Channels in Epilepsy 期刊论文 CNS & neurological disorders drug targets, 2018, 卷号: 17, 页码: 272-279 作者:  Zhu Yudan[1];  Zhang Shuzhang[2];  Feng Yijun[3];  Xiao Qian[4];  Cheng Jiwei[5] 收藏  |  浏览/下载：6/0  |  提交时间：2019/04/24 Action potential  BK channel  auxiliary subunit  epilepsy  large conductance  specific modulator.   One-step generation of complete gene knockout mice and monkeys by CRISPR/Cas9-mediated gene editing with multiple sgRNAs 期刊论文 CELL RESEARCH, 2017, 卷号: 27, 页码: 933-945 作者:  Zuo, Erwei[1];  Cai, Yi-Jun[2];  Li, Kui[3];  Wei, Yu[4];  Wang, Bang-An[5] 收藏  |  浏览/下载：22/0  |  提交时间：2019/04/24 complete gene knockout  CRISPR/Cas9  multiple sgRNAs   Study on a mixed verification strategy for IP-based SoC design 会议论文 2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, HDP'05, 2005-06-27 作者:  Chen, Wenwei[1];  Zhang, Jinyi[2];  Li, Jiao[3];  Ren, Xiaojun[4];  Liu, Jiwei[5] 收藏  |  浏览/下载：5/0  |  提交时间：2019/05/10 Study on a mixed verification strategy for IP-based SoC design 会议论文 Proceedings of the Seventh IEEE CPMT Conference on High Density Microsystem Design, Packaging and Failure Analysis (HDP'05) 作者:  Chen Wenwei[1];  Zhang Jinyi[2];  Li Jiao[3];  Ren Xiaojun[4];  Liu Jiwei[5] 收藏  |  浏览/下载：3/0  |  提交时间：2019/05/10 SoC  IP core  verification platfrom  HW/SW co-verification   Study on a mixed verification strategy for IP-based SoC design 会议论文 Proceedings of the Seventh IEEE CPMT Conference on High Density Microsystem Design, Packaging and Failure Analysis (HDP'05) 作者:  Chen Wenwei[1];  Zhang Jinyi[2];  Li Jiao[3];  Ren Xiaojun[4];  Liu Jiwei[5] 收藏  |  浏览/下载：3/0  |  提交时间：2019/05/10 SoC  IP core  verification platfrom  HW/SW co-verification   Study on a mixed verification strategy for IP-based SoC design 会议论文 Proceedings of the Seventh IEEE CPMT Conference on High Density Microsystem Design, Packaging and Failure Analysis (HDP'05) 作者:  Chen Wenwei[1];  Zhang Jinyi[2];  Li Jiao[3];  Ren Xiaojun[4];  Liu Jiwei[5] 收藏  |  浏览/下载：3/0  |  提交时间：2019/05/10 SoC  IP core  verification platfrom  HW/SW co-verification   Study on a mixed verification strategy for IP-based SoC design 会议论文 Proceedings of the Seventh IEEE CPMT Conference on High Density Microsystem Design, Packaging and Failure Analysis (HDP'05) 作者:  Chen Wenwei[1];  Zhang Jinyi[2];  Li Jiao[3];  Ren Xiaojun[4];  Liu Jiwei[5] 收藏  |  浏览/下载：10/0  |  提交时间：2019/05/10 SoC  IP core  verification platfrom  HW/SW co-verification