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科研机构
北京大学 [39]
厦门大学 [1]
内容类型
其他 [40]
发表日期
2016 [6]
2015 [9]
2014 [2]
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Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics
其他
2016-01-01
Wang, Yuan
;
Liu, Yuequan
;
Jiang, Mengyin
;
Jia, Song
;
Zhang, Xing
收藏
  |  
浏览/下载:3/0
  |  
提交时间:2017/12/03
20 GS/s Photonic Analog-to-Digital Converter Using Optical Comb Based on an Optoelectronic Oscillator
其他
2016-01-01
Peng, Huanfa
;
Peng, Xiaofeng
;
Xu, Yongchi
;
Zhang, Cheng
;
Chen, Yuanxiang
;
Zhu, Lixin
;
Hu, Weiwei
;
Chen, Zhangyuan
收藏
  |  
浏览/下载:4/0
  |  
提交时间:2017/12/03
JITTER
ADC
Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics
其他
2016-01-01
Wang, Yuan
;
Liu, Yuequan
;
Jiang, Mengyin
;
Jia, Song
;
Zhang, Xing
收藏
  |  
浏览/下载:2/0
  |  
提交时间:2017/12/03
quadrupler
delay-locked loop (DLL)
eight-phase-clock generator
edge-combiner
wide operating range
fast locking
MULTIPLIER
A Novel Low-Power Readout Structure with 1/2 Sub-Scan Time-Delay-Integration and DLL-Based A/D for 1024x6 Infrared Focal Plane Array
其他
2016-01-01
Liu, Benyuanyi
;
Lu, Wengao
;
Liu, Dahe
;
Yu, Shanzhe
;
Zhang, Yacong
;
Chen, Zhongjian
收藏
  |  
浏览/下载:2/0
  |  
提交时间:2017/12/03
Time-delay-integration (TDI)
sub-scan
Infrared Focal Plane Array (IRFPA)
Delay-locked-loop (DLL)
Analog-to-digital converter (ADC)
CMOS IMAGE SENSOR
A 7.9 fJ/conversion-step 10-bit 125 MS/s SAR ADC with Simplified Power-efficient Digital Control Logic
其他
2016-01-01
Mingxiao He
;
Fan Yang
;
Xiucheng Hao
;
Le Ye
;
Huailin Liao
收藏
  |  
浏览/下载:3/0
  |  
提交时间:2017/12/03
capacitor
consuming
switching
converter
sandwich
figure
analog
monotonic
prototype
successive
capacitor
consuming
switching
converter
sandwich
figure
analog
monotonic
prototype
successive
A 16GS/s 6-bit Current-Steering DAC with TI topology in 40nm CMOS
其他
2016-01-01
Bao Li
;
Long Zhao
;
Chenxi Deng
;
Yuhua Cheng
收藏
  |  
浏览/下载:3/0
  |  
提交时间:2017/12/03
topology
segmented
SFDR
steering
analog
converter
programmed
clock
dissipation
decoder
topology
segmented
SFDR
steering
analog
converter
programmed
clock
dissipation
decoder
Digital servo system based on FPGA for optically pumped magnetometer
其他
2015-01-01
Zhou, Sheng
;
Liu, Chang
;
Wang, Yanhui
;
Zhang, Daonong
收藏
  |  
浏览/下载:4/0
  |  
提交时间:2017/12/03
180.5Mbps-8Gbps DLL-Based Clock and Data Recovery Circuit with Low Jitter Performance
其他
2015-01-01
Liu, Yuequan
;
Wang, Yuan
;
Jia, Song
;
Zhang, Xing
收藏
  |  
浏览/下载:5/0
  |  
提交时间:2017/12/03
Clock and data recovery (CDR)
wide-range
delay-locked loop (DLL)
low jitter
time-to-digital converter (TDC)
A 15-bit two-step pixel-level ADC for 17m-pitch low-power and high-dynamic-range IRFPA
其他
2015-01-01
Zhang, Luya
;
Lyu, Binbin
;
Lu, Wengao
;
Liu, Dahe
;
Zhao, Meng
;
Zhang, Yacong
;
Chen, Zhongjian
收藏
  |  
浏览/下载:3/0
  |  
提交时间:2017/12/03
A 15-bit Two-Step Pixel-Level ADC for 17 mu m-Pitch Low-Power and High-Dynamic-Range IRFPA
其他
2015-01-01
Zhang, Luya
;
Lyu, Binbin
;
Lu, Wengao
;
Liu, Dahe
;
Zhao, Meng
;
Zhang, Yacong
;
Chen, Zhongjian
收藏
  |  
浏览/下载:6/0
  |  
提交时间:2017/12/03
analog-to-digital converter (ADC)
pixel-level
Infrared Focal Plane Array (IRRPA)
low power
dynamic range
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