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A resource-saving dual channel time-to-digital converter with shared tapped delay line in FPGAs 期刊论文
JOURNAL OF INSTRUMENTATION, 2021, 卷号: 16
作者:  Jiao, Y.;  Zhang, Q.;  Chen, W.;  Zhou, L.;  Chen, C.
收藏  |  浏览/下载:11/0  |  提交时间:2021/08/31


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