| 题名 | 全数字锁相环的设计与实现 |
| 作者 | 李肃刚 |
| 学位类别 | 硕士 |
| 答辩日期 | 2005-05-31 |
| 授予单位 | 中国科学院沈阳自动化研究所 |
| 授予地点 | 中国科学院沈阳自动化研究所 |
| 导师 | 杨志家 |
| 关键词 | 全数字锁相环 鉴频鉴相器 环路滤波器 数控振荡器 验证 |
| 其他题名 | The Design and Implementation of All-Digital Phase-Locked Loop |
| 学位专业 | 机械电子工程 |
| 中文摘要 | 锁相环路系统是一种输出信号在频率上能够与输入参考信号同步的电路系统，它是现代电路中的一个非常重要的模块。由于锁相环具有捕获、跟踪以及窄带滤波的能力，因此它被广泛地应用于控制、航天、通信以及微处理器等众多领域。锁相环在集成电路中的应用，主要为片内其他器件提供稳定的、高频的时钟信号。随着集成电路的发展和SoC技术的出现，锁相环已经成为超大规模集成电路中必不可少的一个模块，因此对锁相环电路的研究与设计具有更加重要的意义。本文详细介绍了一种用于嵌入集成电路中的全数字锁相环路系统的设计与实现。本文首先对锁相技术的发展历史和研究现状作了简单的介绍，然后从模拟锁相环路系统的数学原理推导出数字锁相环的数学模型，并以此为基础，介绍了在全数字锁相环路系统中常用的全数字部件的工作原理。根据这些全数字锁相环路部件，并分析原有设计的不足之处，设计了一个能用硬件描述语言实现的全数字锁相环路系统。该系统具有以下特点：具有移植性，增加了设计的灵活性；增加鉴频模块，可对在锁定范围内的未知输入信号进行鉴频锁定；使用PFD作为鉴频器，增加了系统的线性鉴相范围。在介绍各个部件的工作原理之后，对环路的工作过程和性能进行了介绍和分析。论文最后在介绍仿真验证的理论知识的基础上，使用计算机仿真验证工具进行了验证，并将设计代码下载到FPGA中，在真实环境中进行了测试。仿真结果显示，系统性能基本达到了预期的目标。系统的最大工作频率达到150MHz，占用了103个查找表和52个寄存器资源。 |
| 索取号 | TN911.8/L35/2005 |
| 英文摘要 | Phase-locked loop (PLL) system is a circuit which can synchronize its output signal with an input reference signal in frequency. It’s a fundamental and very important module in the modern circuits. Because of its ability of tracking, acquisition and operating as a narrow-band filter, PLL is widely used in many fields such control, astronautics, communication, microprocessor, and so on. One important application of PLL in integrated circuit is to provide on-chip stabled and high frequency clock for the system. With the development of integrated circuit and the emergence of SoC (System on a Chip) technology, PLL has played so indispensable in VLSI (very large scale integrated) circuits that it is worth researching and designing. In this dissertation, the design and implementation of all-digital phase-locked loop (ADPLL) utilized in ICs are described in detail. First of all, the history of the phase locked technology and the actuality of researches are introduced. Then we educe the mathematical model of the digital-PLL (DPLL) from the mathematical principle of the analog PLL system, and the principle of the popular modules of ADPLL which are based on the mathematical model is introduced. Through analysing the disadvantages of the present designs, we design an ADPLL system described in HDL (Hardware Describe Language). The system has so good migrated that increasing flexibleness of design. In the system, the module of frequency detector is added which can detect the unknown-frequency signal within the locked-in range; and the range of the linean phase-detecting is enlarged by using the PFD (Phase Frequency Detector) to replace the XORPD and ECPD. After introducing the principle of the modules, the work proceeding of the system is introduced and the characters of the system are analysed. At last, we verify the system and modules by simulation tools after introducing the theory of verification, and emulate the system by downloading the code into FPGA (Field programming Gate Array). The results show that the system can meet the expectation. The maximum frequency is 150MHz and the engrossed source is 103 LUTs (Look-Up Table) and 52 registers. |
| 语种 | 中文 |
| 产权排序 | 1 |
| 公开日期 | 2012-08-29 |
| 分类号 | TN911.8 |
| 内容类型 | 学位论文 |
| 源URL | [http://ir.sia.ac.cn/handle/173321/9472]  |
| 专题 | 沈阳自动化研究所_工业信息学研究室_工业控制系统研究室 |
| 推荐引用方式 GB/T 7714 | 李肃刚. 全数字锁相环的设计与实现[D]. 中国科学院沈阳自动化研究所. 中国科学院沈阳自动化研究所. 2005. |
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