Ultracompact linear on-chip silicon optical logic gates with phase insensitivity | |
Wang, C ; Li, ZY | |
刊名 | EPL
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2013 | |
卷号 | 103期号:6 |
ISSN号 | 0295-5075 |
通讯作者 | Wang, C (reprint author), Chinese Acad Sci, Inst Phys, Lab Opt Phys, POB 603, Beijing 100190, Peoples R China. |
中文摘要 | All-optical integrated circuits for computing and information processing have been pursued for decades as a potential strategy to overcome the speed limitations intrinsic to electronics. However, feasible on-chip integrated logic units and devices still have been limited by their size, quality, scalability, and reliability. Here we analyse all-passive on-chip optical AND and NAND logic gates made from a directional emitting cavity connecting two ultrasmall photoniccrystal heterojunction diodes. The measured transmission spectra show more than 10 dB contrast of the logic transport with a high phase tolerance, agreeing well with numerical simulations. The building of linear, passive, and ultracompact silicon optical logic gates might pave the way to construct novel nanophotonic on-chip processor architectures for future optical computing technologies. Copyright (C) EPLA, 2013 |
资助信息 | National Basic Research Foundation of China [2011CB922002]; Knowledge Innovation Program of the Chinese Academy of Sciences [Y1V2013L11]; International Science and Technology Cooperation Program of China [2012DFA10730]; Natural Science Foundation of Shandong Province of China [ZR2010FM039] |
语种 | 英语 |
公开日期 | 2014-01-17 |
内容类型 | 期刊论文 |
源URL | [http://ir.iphy.ac.cn/handle/311004/57640] ![]() |
专题 | 物理研究所_物理所公开发表论文_物理所公开发表论文_期刊论文 |
推荐引用方式 GB/T 7714 | Wang, C,Li, ZY. Ultracompact linear on-chip silicon optical logic gates with phase insensitivity[J]. EPL,2013,103(6). |
APA | Wang, C,&Li, ZY.(2013).Ultracompact linear on-chip silicon optical logic gates with phase insensitivity.EPL,103(6). |
MLA | Wang, C,et al."Ultracompact linear on-chip silicon optical logic gates with phase insensitivity".EPL 103.6(2013). |
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