Compact Model for Double-Gate Tunnel FETs With Gate-Drain Underlap | |
Xu, Peng2; Lou, Haijun1,2; Zhang, Lining3; Yu, Zhonghua2; Lin, Xinnan2 | |
刊名 | IEEE TRANSACTIONS ON ELECTRON DEVICES |
2017-12 | |
卷号 | 64期号:12页码:5242-5248 |
关键词 | Ambipolar current compact model gate-drainunderlap tunneling field-effect transistor (TFET) |
ISSN号 | 0018-9383 |
DOI | 10.1109/TED.2017.2762861 |
英文摘要 | A compact model for double-gate tunnel FETs (TFETs) with gate-drain underlap (DG u-TFET) is proposed which accounts for the alleviation of ambipolar current and Miller capacitance (C-dg) compared with double-gate tunnel FETs (DG TFET). The ON-state current degradation caused by the underlap is reproduced by extending the ideal DG TFET model with an effective resistance between the channel and the drain. Based on the device surface potential, the terminal charge model is developedwhich enables the possibilityof circuit simulation and the terminal capacitance is further derived from the definition. This model captures the electrical characteristics of DG u-TFET explicitly and good agreement is achieved compared with TCAD simulation. After the model is implemented into HSPICE, an inverter is established and successfully simulated without convergence problem. |
WOS研究方向 | Engineering ; Physics |
语种 | 英语 |
出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
WOS记录号 | WOS:000417727500062 |
内容类型 | 期刊论文 |
源URL | [http://119.78.100.223/handle/2XXMBERH/33010] |
专题 | 兰州理工大学 |
作者单位 | 1.Lanzhou Univ Technol, Sch Sci, Lanzhou 730050, Gansu, Peoples R China; 2.Peking Univ, Shenzhen Key Lab Adv Electron Device & Integrat, Sch Elect & Comp Engn, Shenzhen Grad Sch, Shenzhen 518055, Peoples R China; 3.Shenzhen Univ, Coll Elect Sci & Technol, Shenzhen 518060, Peoples R China |
推荐引用方式 GB/T 7714 | Xu, Peng,Lou, Haijun,Zhang, Lining,et al. Compact Model for Double-Gate Tunnel FETs With Gate-Drain Underlap[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES,2017,64(12):5242-5248. |
APA | Xu, Peng,Lou, Haijun,Zhang, Lining,Yu, Zhonghua,&Lin, Xinnan.(2017).Compact Model for Double-Gate Tunnel FETs With Gate-Drain Underlap.IEEE TRANSACTIONS ON ELECTRON DEVICES,64(12),5242-5248. |
MLA | Xu, Peng,et al."Compact Model for Double-Gate Tunnel FETs With Gate-Drain Underlap".IEEE TRANSACTIONS ON ELECTRON DEVICES 64.12(2017):5242-5248. |
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