IP core design for parameterized (2, 1, N) convolutional encodes

CORC > 沈阳自动化研究所 > 中国科学院沈阳自动化研究所 > 工业控制网络与系统研究室

	IP core design for parameterized (2, 1, N) convolutional encodes
	Duan MQ(段茂强); Huang XL(黄晓莉); Yang ZJ(杨志家)
	2013
会议名称	2013 2nd International Conference on Measurement, Instrumentation and Automation, ICMIA 2013
会议日期	April 23-24, 2013
会议地点	Guilin, China
关键词	CMOS integrated circuits Convolution Parameterization
页码	1463-1468
中文摘要	In this paper, we design and implement general parameterized IP (Intellectual Property) cores of convolutional encoder with SMIC 0.35μm CMOS technology, serial structure and parallel structure respectively. And analyze each of the power dissipation using Synopsys PTPX tool. The result shows the parallel circuit structure saves 14 percent power dissipation compared to that of serial circuit structure, with the same encode radio. Meanwhile, computing speed of parallel structure with 8-bit parallelism is 8 times than that of serial structure under the same clock frequency. Certainly, serial circuit structure has their particular characters such as easily realized and less resource consumption. © (2013) Trans Tech Publications, Switzerland.
收录类别	EI ; CPCI（ISTP）
产权排序	1
会议主办者	Korea Maritime University; Hong Kong Industrial Technology Research Centre; Inha University
会议录	Applied Mechanics and Materials
会议录出版者	Trans Tech Publications Ltd
会议录出版地	Zurich-Durnten, Switzerland
语种	英语
ISSN号	1660-9336
ISBN号	978-3-03785-751-9
WOS记录号	WOS:000328521200280
内容类型	会议论文
源URL	[http://ir.sia.cn/handle/173321/12427]
专题	沈阳自动化研究所_工业控制网络与系统研究室
推荐引用方式 GB/T 7714	Duan MQ,Huang XL,Yang ZJ. IP core design for parameterized (2, 1, N) convolutional encodes[C]. 见:2013 2nd International Conference on Measurement, Instrumentation and Automation, ICMIA 2013. Guilin, China. April 23-24, 2013.