A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

CORC > 半导体研究所 > 中国科学院半导体研究所 > 中国科学院半导体研究所（2009年前）

	A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC
	Dai, FF ; Ni, WN ; Yin, S ; Jaeger, RC
	2006
会议名称	symposium on vlsi circuits
会议日期	jun 16-18, 2005
会议地点	kyoto, japan
关键词	CMOS integrated circuits
页码	41 (4): 839-850
通讯作者	dai, ff, auburn univ, dept elect & comp engn, auburn, al 36849 usa. 电子邮箱地址: fasterdai@auburn.edu ; wnni@red.semi.ac.cn ; yshi@red.semi.ac.cn ; jaeger@eng.auburn.edu
中文摘要	this paper presents a direct digital frequency synthesizer (ddfs) with a 16-bit accumulator, a fourth-order phase domain single-stage delta sigma interpolator, and a 300-ms/s 12-bit current-steering dac based on the q(2) random walk switching scheme. the delta sigma interpolator is used to reduce the phase truncation error and the rom size. the implemented fourth-order single-stage delta sigma noise shaper reduces the effective phase bits by four and reduces the rom size by 16 times. the ddfs prototype is fabricated in a 0.35-mu m cmos technology with active area of 1.11 mm(2) including a 12-bit dac. the measured ddfs spurious-free dynamic range (sfdr) is greater than 78 db using a reduced rom with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). the total power consumption of the ddfs is 200)mw with a 3.3-v power supply.
英文摘要	this paper presents a direct digital frequency synthesizer (ddfs) with a 16-bit accumulator, a fourth-order phase domain single-stage delta sigma interpolator, and a 300-ms/s 12-bit current-steering dac based on the q(2) random walk switching scheme. the delta sigma interpolator is used to reduce the phase truncation error and the rom size. the implemented fourth-order single-stage delta sigma noise shaper reduces the effective phase bits by four and reduces the rom size by 16 times. the ddfs prototype is fabricated in a 0.35-mu m cmos technology with active area of 1.11 mm(2) including a 12-bit dac. the measured ddfs spurious-free dynamic range (sfdr) is greater than 78 db using a reduced rom with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). the total power consumption of the ddfs is 200)mw with a 3.3-v power supply.; zhangdi于2010-03-29批量导入; zhangdi于2010-03-29批量导入; japan soc appl phys.; ieee solid-state circuits soc.; inst elect informat & commun engeers japan.; ieee elect dev soc.; auburn univ, dept elect & comp engn, auburn, al 36849 usa; chinese acad sci, inst semicond, beijing 100083, peoples r china
收录类别	其他
会议主办者	japan soc appl phys.; ieee solid-state circuits soc.; inst elect informat & commun engeers japan.; ieee elect dev soc.
会议录	ieee journal of solid-state circuits
会议录出版者	ieee-inst electrical electronics engineers inc ; 445 hoes lane, piscataway, nj 08855 usa
会议录出版地	445 hoes lane, piscataway, nj 08855 usa
学科主题	人工智能
语种	英语
ISSN号	0018-9200
内容类型	会议论文
源URL	[http://ir.semi.ac.cn/handle/172111/10036]
专题	半导体研究所_中国科学院半导体研究所（2009年前）
推荐引用方式 GB/T 7714	Dai, FF,Ni, WN,Yin, S,et al. A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC[C]. 见:symposium on vlsi circuits. kyoto, japan. jun 16-18, 2005.