The design and verification of FPGA CAD toolset

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	The design and verification of FPGA CAD toolset
	Zhou HB ; N, MH ; Chen S ; Liu ZL
	2007
会议名称	international symposium on integrated circuits
会议日期	sep 26-28, 2007
会议地点	singapore`, singapore
页码	vols 1 and 2: 461-464
通讯作者	zhou, hb, chinese acad sci, inst semicond, pob 912, beijing 100083, peoples r china.
中文摘要	this paper introduces a complete cad toolset for the implementation of digital logic in a field-programmable gate array (fpga) platform. compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. the fpga cad tool verification flow using formality is presented in detail. using plug-in technology, we have developed an integrated fpga design kit to incorporate all tools together.
英文摘要	this paper introduces a complete cad toolset for the implementation of digital logic in a field-programmable gate array (fpga) platform. compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. the fpga cad tool verification flow using formality is presented in detail. using plug-in technology, we have developed an integrated fpga design kit to incorporate all tools together.; zhangdi于2010-03-09批量导入; zhangdi于2010-03-09批量导入; [zhou, huabing; ni, minghao; chen, stanley; liu, zhongli] chinese acad sci, inst semicond, beijing 100083, peoples r china
收录类别	其他
会议录	2007 international symposium on integrated circuits
会议录出版者	ieee ; 345 e 47th st, new york, ny 10017 usa
会议录出版地	345 e 47th st, new york, ny 10017 usa
学科主题	微电子学
语种	英语
ISBN号	978-1-4244-0796-5
内容类型	会议论文
源URL	[http://ir.semi.ac.cn/handle/172111/7778]
专题	半导体研究所_中国科学院半导体研究所（2009年前）
推荐引用方式 GB/T 7714	Zhou HB,N, MH,Chen S,et al. The design and verification of FPGA CAD toolset[C]. 见:international symposium on integrated circuits. singapore`, singapore. sep 26-28, 2007.