A Chaotic IP Watermarking in Physical Layout Level Based on FPGA | |
Liang, W; Sun, XM; Xia, ZH; Sun, DC; Long, J | |
刊名 | Radioengineering
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2011 | |
卷号 | Vol.20 No.1页码:118-125 |
关键词 | IP reuse technology FPGA chaotic map LUT IP watermarking |
ISSN号 | 1210-2512 |
URL标识 | 查看原文 |
公开日期 | [db:dc_date_available] |
内容类型 | 期刊论文 |
URI标识 | http://www.corc.org.cn/handle/1471x/6514601 |
专题 | 湖南大学 |
作者单位 | 1.Hunan Univ, Sch Comp & Commun, Changsha 410082, Hunan, Peoples R China 增强组织信息的名称 Hunan University 2.Hunan Univ Sci & Technol, Sch Engn & Comp Sci, Xiangtan 411201, Peoples R China 增强组织信息的名称 Hunan University of Science & Technology |
推荐引用方式 GB/T 7714 | Liang, W,Sun, XM,Xia, ZH,et al. A Chaotic IP Watermarking in Physical Layout Level Based on FPGA[J]. Radioengineering,2011,Vol.20 No.1:118-125. |
APA | Liang, W,Sun, XM,Xia, ZH,Sun, DC,&Long, J.(2011).A Chaotic IP Watermarking in Physical Layout Level Based on FPGA.Radioengineering,Vol.20 No.1,118-125. |
MLA | Liang, W,et al."A Chaotic IP Watermarking in Physical Layout Level Based on FPGA".Radioengineering Vol.20 No.1(2011):118-125. |
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