QQ客服 官方微博 反馈留言

	A NEW DFT ARCHITECTURE TO REDUCE TEST DATA VOLUME AND TEST APPLICATION TIME
	Ling, Zhang; Jishun, Kuang; Junjin, Mei
刊名	ENGINEERING REVIEW
	2016
卷号	Vol.36 No.3页码:197-202
关键词	Test data compression Integrated circuits Broadcast architecture Design for test
ISSN号	1330-9587
URL标识	查看原文
公开日期	[db:dc_date_available]
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/6073705
专题	湖南大学
作者单位	1.College of Information Science and Engineering, Hunan University, Changsha 2.410082, China 3.School of Computer, Hubei Polytechnic University, Huangshi 4.435003, China
推荐引用方式 GB/T 7714	Ling, Zhang,Jishun, Kuang,Junjin, Mei. A NEW DFT ARCHITECTURE TO REDUCE TEST DATA VOLUME AND TEST APPLICATION TIME[J]. ENGINEERING REVIEW,2016,Vol.36 No.3:197-202.
APA	Ling, Zhang,Jishun, Kuang,&Junjin, Mei.(2016).A NEW DFT ARCHITECTURE TO REDUCE TEST DATA VOLUME AND TEST APPLICATION TIME.ENGINEERING REVIEW,Vol.36 No.3,197-202.
MLA	Ling, Zhang,et al."A NEW DFT ARCHITECTURE TO REDUCE TEST DATA VOLUME AND TEST APPLICATION TIME".ENGINEERING REVIEW Vol.36 No.3(2016):197-202.

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。