A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI | |
Wang, Y.; Cai, H.; Naviner, L. A. B.; Zhao, X. X.; Zhang, Y.; Slimani, M.; Klein, J. O.; Zhao, W. S. | |
2016 | |
会议名称 | 27th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF) |
会议日期 | 2016-09-01 |
会议地点 | Halle, GERMANY |
关键词 | Process variation Variability analysis Magnetic flip-flop Asymmetrical forward body bias FDSOI |
卷号 | 64 |
页码 | 26-30 |
收录类别 | SCIE ; CPCI-S |
URL标识 | 查看原文 |
WOS记录号 | WOS:000386401600005 |
内容类型 | 会议论文 |
URI标识 | http://www.corc.org.cn/handle/1471x/5955014 |
专题 | 北京航空航天大学 |
推荐引用方式 GB/T 7714 | Wang, Y.,Cai, H.,Naviner, L. A. B.,et al. A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI[C]. 见:27th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF). Halle, GERMANY. 2016-09-01. |
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