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	A fault-tolerant architecture with error correcting code for the instruction-level temporal redundancy
	Yan, Chao; Dai, Hongjun; Chen, Tianzhou; Qiu, Meikang
刊名	Proceedings - IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, EUC 2010
	2010
页码	797-803
关键词	Double execution Fast error correcting code Fault tolerance Instruction reuse buffer Soft errors
DOI	10.1109/EUC.2010.124
会议名称	IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, EUC 2010
URL标识	查看原文
会议日期	11 December 2010 through 13 December 2010
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/5513087
专题	山东大学
作者单位	1.Dept. of Computer Science and Technology, Shandong University, Jinan, China 2.Dept. of Electrical and Compute
推荐引用方式 GB/T 7714	Yan, Chao,Dai, Hongjun,Chen, Tianzhou,et al. A fault-tolerant architecture with error correcting code for the instruction-level temporal redundancy[J]. Proceedings - IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, EUC 2010,2010:797-803.
APA	Yan, Chao,Dai, Hongjun,Chen, Tianzhou,&Qiu, Meikang.(2010).A fault-tolerant architecture with error correcting code for the instruction-level temporal redundancy.Proceedings - IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, EUC 2010,797-803.
MLA	Yan, Chao,et al."A fault-tolerant architecture with error correcting code for the instruction-level temporal redundancy".Proceedings - IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, EUC 2010 (2010):797-803.

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