FPGA verification for memory link interface of many-core processor | |
Zhou, Hongwei; Xu, Shi; Wang, Zhongyi; Yang, Qianming; Feng, Quanyou; Deng, Rangyu; Dou, Qiang | |
刊名 | Journal of National University of Defense Technology
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2018 | |
卷号 | Vol.40 No.3页码:176-182 |
ISSN号 | 1001-2486 |
URL标识 | 查看原文 |
公开日期 | [db:dc_date_available] |
内容类型 | 期刊论文 |
URI标识 | http://www.corc.org.cn/handle/1471x/5468485 |
专题 | 湖南大学 |
作者单位 | 1.llege of Computer, National University of Defense Technology, Changsha 2.410073, China 3.College of Computer Science and Electronic Engineering, Hunan University, Changsha 4.410082, China |
推荐引用方式 GB/T 7714 | Zhou, Hongwei,Xu, Shi,Wang, Zhongyi,et al. FPGA verification for memory link interface of many-core processor[J]. Journal of National University of Defense Technology,2018,Vol.40 No.3:176-182. |
APA | Zhou, Hongwei.,Xu, Shi.,Wang, Zhongyi.,Yang, Qianming.,Feng, Quanyou.,...&Dou, Qiang.(2018).FPGA verification for memory link interface of many-core processor.Journal of National University of Defense Technology,Vol.40 No.3,176-182. |
MLA | Zhou, Hongwei,et al."FPGA verification for memory link interface of many-core processor".Journal of National University of Defense Technology Vol.40 No.3(2018):176-182. |
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