VFSim: Concurrent fault simulation at register transfer level

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	VFSim: Concurrent fault simulation at register transfer level
	Shen, L
刊名	JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
	2005-03-01
卷号	20 期号:2 页码:175-186
关键词	high-level testing Verilog RTL circuit modeling fault model concurrent fault simulation
ISSN号	1000-9000
英文摘要	VLSI testing is being pushed to the high-level based technology. In this paper a Verilog Register transfer level Model (VRM) for integrated circuits is proposed. The model provides a text format file, which is convenient and more practical for developing succeeding Register Transfer Level (RTL) test tools, such as fault simulation, test pattern generation and so forth. Based on the VRM, an RTL concurrent fault simulation approach is presented. After RTL fault models and super faults defined, the concurrent fault simulation algorithm is given. The corresponding RTL concurrent fault simulator, VFSim, was implemented. The initial experiments show that the RTL fault simulator is efficient for VLSI circuits.
WOS研究方向	Computer Science
语种	英语
出版者	SCIENCE PRESS
WOS记录号	WOS:000227919000004
内容类型	期刊论文
源URL	[http://119.78.100.204/handle/2XEOYT63/10219]
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Shen, L
作者单位	Chinese Acad Sci, Inst Comp Technol, Beijing 100080, Peoples R China
推荐引用方式 GB/T 7714	Shen, L. VFSim: Concurrent fault simulation at register transfer level[J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,2005,20(2):175-186.
APA	Shen, L.(2005).VFSim: Concurrent fault simulation at register transfer level.JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,20(2),175-186.
MLA	Shen, L."VFSim: Concurrent fault simulation at register transfer level".JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 20.2(2005):175-186.