CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs

doi:10.1109/TC.2017.2776272

CORC > 计算技术研究所 > 中国科学院计算技术研究所 > 中国科学院计算技术研究所期刊论文 > 英文

	CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs
	Xie, Xiaolong 1; Liang, Yun 1; Li, Xiuhong 1; Wu, Yudong 1; Sun, Guangyu 1; Wang, Tao 1; Fan, Dongrui 2
刊名	IEEE TRANSACTIONS ON COMPUTERS
	2018-06-01
卷号	67 期号:6 页码:890-897
关键词	GPGPU memory hierarchy compilers
ISSN号	0018-9340
DOI	10.1109/TC.2017.2776272
英文摘要	The key to the high performance on GPUs lies in the massive threading to enable thread switching and hide long latencies. CPUs are equipped with a large register file to enable fast context switch. However, thread throttling techniques that are designed to mitigate cache contention, lead to under-utilization of registers. Register allocation is a significant factor for performance as it not just determines the single-thread performance, but indirectly affects the TLP. In this paper, we propose Coordinated Register Allocation and Thread-level parallelism (CRAT) to explore the optimization space of register allocation and TLP management on GPUs. CRAT employs both compile-time(CRAT-static) and run-time techniques(CRAT-dyn) to exhaust the design space. CRAT-static works statically to explore TLP and register allocation trade-off and CRAT-dyn exploits dynamic register allocation for further improvement. Experiments indicate that CRAT-static achieves an average 1.25X speedup over existing TLP management technique. On four register-limited applications, CRAT-dyn further improves the performance speedup of CRAT-static from 1.51X to 1.70X.
资助项目	Natural Science Foundation of China[61672048]
WOS研究方向	Computer Science ; Engineering
语种	英语
出版者	IEEE COMPUTER SOC
WOS记录号	WOS:000431902600010
内容类型	期刊论文
源URL	[http://119.78.100.204/handle/2XEOYT63/5354]
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Xie, Xiaolong
作者单位	1.Peking Univ, Sch EECS, Ctr Energy Efficient Comp & Applicat, Beijing 100080, Peoples R China 2.Chinese Acad Sci, Inst Comp Technol, Beijing 100864, Peoples R China
推荐引用方式 GB/T 7714	Xie, Xiaolong,Liang, Yun,Li, Xiuhong,et al. CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs[J]. IEEE TRANSACTIONS ON COMPUTERS,2018,67(6):890-897.
APA	Xie, Xiaolong.,Liang, Yun.,Li, Xiuhong.,Wu, Yudong.,Sun, Guangyu.,...&Fan, Dongrui.(2018).CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs.IEEE TRANSACTIONS ON COMPUTERS,67(6),890-897.
MLA	Xie, Xiaolong,et al."CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs".IEEE TRANSACTIONS ON COMPUTERS 67.6(2018):890-897.