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	Analysis and Design of a Digital Phase-Locked Loop for Single-Phase Grid-Connected Power Conversion Systems
	Zhang, Qi; Sun, Xiang-Dong; Zhong, Yan-Ru; Matsui, Mikihiko; Ren, Bi-Ying
	2011
卷号	58页码:3581-3592
关键词	Digital phase-locked loop (DPLL) grid-connected inverter p-q theory variable step-size phase correction
ISSN号	0278-0046
DOI	10.1109/TIE.2010.2087295
URL标识	查看原文
WOS记录号	WOS:000293685700045
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/5035995
专题	西安理工大学
推荐引用方式 GB/T 7714	Zhang, Qi,Sun, Xiang-Dong,Zhong, Yan-Ru,et al. Analysis and Design of a Digital Phase-Locked Loop for Single-Phase Grid-Connected Power Conversion Systems[J],2011,58:3581-3592.
APA	Zhang, Qi,Sun, Xiang-Dong,Zhong, Yan-Ru,Matsui, Mikihiko,&Ren, Bi-Ying.(2011).Analysis and Design of a Digital Phase-Locked Loop for Single-Phase Grid-Connected Power Conversion Systems.,58,3581-3592.
MLA	Zhang, Qi,et al."Analysis and Design of a Digital Phase-Locked Loop for Single-Phase Grid-Connected Power Conversion Systems".58(2011):3581-3592.

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