A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs | |
Li, Yanbin; Tang, Ming; Li, Yuguang; Zhang, Huanguo | |
刊名 | Integration
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2019 | |
ISSN号 | 0167-9260 |
DOI | 10.1016/j.vlsi.2019.09.003 |
URL标识 | 查看原文 |
收录类别 | EI |
语种 | 英语 |
内容类型 | 期刊论文 |
URI标识 | http://www.corc.org.cn/handle/1471x/4232267 |
专题 | 武汉大学 |
推荐引用方式 GB/T 7714 | Li, Yanbin,Tang, Ming,Li, Yuguang,et al. A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs[J]. Integration,2019. |
APA | Li, Yanbin,Tang, Ming,Li, Yuguang,&Zhang, Huanguo.(2019).A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs.Integration. |
MLA | Li, Yanbin,et al."A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs".Integration (2019). |
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