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	A High-Speed 2-bit/Cycle SAR ADC With Time-Domain Quantization
	Qiu, Lei; Yang, Chuanshi; Wang, Keping*; Zheng, Yuanjin
刊名	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
	2018
卷号	26期号:10页码:2175-2179
关键词	2 bit/cycle analog-to-digital converter (ADC) nonbinary successive approximation register (SAR) time-domain quantization
ISSN号	1063-8210
DOI	10.1109/TVLSI.2018.2837030
URL标识	查看原文
WOS记录号	WOS:000446332500033
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/3400968
专题	武汉理工大学
作者单位	1.[Yang, Chuanshi 2.Zheng, Yuanjin 3.Qiu, Lei] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore.
推荐引用方式 GB/T 7714	Qiu, Lei,Yang, Chuanshi,Wang, Keping*,et al. A High-Speed 2-bit/Cycle SAR ADC With Time-Domain Quantization[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2018,26(10):2175-2179.
APA	Qiu, Lei,Yang, Chuanshi,Wang, Keping*,&Zheng, Yuanjin.(2018).A High-Speed 2-bit/Cycle SAR ADC With Time-Domain Quantization.IEEE Transactions on Very Large Scale Integration (VLSI) Systems,26(10),2175-2179.
MLA	Qiu, Lei,et al."A High-Speed 2-bit/Cycle SAR ADC With Time-Domain Quantization".IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26.10(2018):2175-2179.

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