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	A novel delay optimization method for a critical path in VLSI design
	Ma, Xiaolong; Wu, Minshun; Xu, Jiangtao; Chen, Guican
刊名	IEICE ELECTRONICS EXPRESS
	2013
卷号	10期号:[db:dc_citation_issue]
关键词	critical path path delay fan-out factor VLSI
ISSN号	1349-2543
DOI	[db:dc_identifier_doi]
URL标识	查看原文
WOS记录号	[DB:DC_IDENTIFIER_WOSID]
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/3306687
专题	西安交通大学
推荐引用方式 GB/T 7714	Ma, Xiaolong,Wu, Minshun,Xu, Jiangtao,et al. A novel delay optimization method for a critical path in VLSI design[J]. IEICE ELECTRONICS EXPRESS,2013,10([db:dc_citation_issue]).
APA	Ma, Xiaolong,Wu, Minshun,Xu, Jiangtao,&Chen, Guican.(2013).A novel delay optimization method for a critical path in VLSI design.IEICE ELECTRONICS EXPRESS,10([db:dc_citation_issue]).
MLA	Ma, Xiaolong,et al."A novel delay optimization method for a critical path in VLSI design".IEICE ELECTRONICS EXPRESS 10.[db:dc_citation_issue](2013).

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