This paper presents a 65nm 1Gb NOR-type Floating-gate Flash memory, in which the cell device and chip circuit are developed and optimized. In order to solve the speed problem of giga-level NOR Flash in the deep sub-micron process, the models of long bit-line and word-line are first given, by which the capacitive and resistive loads could be estimated. Based on that, the read path and key modules are optimized to enhance the chip access property and reliability.