Design and verification of universal evaluation system for single event effect sensitivity measurement in very-large-scale integrated circuits

doi:10.1587/elex.16.20190196

	Design and verification of universal evaluation system for single event effect sensitivity measurement in very-large-scale integrated circuits
	Xu, Liewei 1; Cai, Chang 2,3; Liu, Tianqi 2,3; Ke, Lingyun 2,3; Yu, Jun 1; Wu, Chang 1
刊名	IEICE ELECTRONICS EXPRESS
	2019-05-25
卷号	16 期号:10 页码:6
关键词	FPGA single event effects heavy ions irradiation
ISSN号	1349-2543
DOI	10.1587/elex.16.20190196
通讯作者	Cai, Chang(caichang@impcas.ac.cn)
英文摘要	A flexible and multipurpose Single Event Effects (SEEs) testing system was developed for evaluating the reliability of nanoscale Very Large Scale Integrated Circuit (VLSI). The accurate detection, comparation and classification of latch-up, upset, and functional interrupt were achieved. In host PC part, two customized software systems were developed, including the Procise for maximal resources occupation and a C-# based visual control interface for real-time communication. For hardware, a motherboard-daughterboard system guaranteed testing performance and kept its compatibility throughout testing. The fault injection and Ta-181(31+) irradiation results indicated the validity of proposed measurements and the stability of hardware operation. Importantly, the high anti-irradiation performance of device was also verified.
资助项目	National Natural Science Foundation of China[11805244] ; National Natural Science Foundation of China[11690041] ; National Natural Science Foundation of China[11675233]
WOS关键词	MITIGATION ; ROBUST
WOS研究方向	Engineering
语种	英语
出版者	IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
WOS记录号	WOS:000470698800009
资助机构	National Natural Science Foundation of China
内容类型	期刊论文
源URL	[http://119.78.100.186/handle/113462/133293]
专题	中国科学院近代物理研究所
通讯作者	Cai, Chang
作者单位	1.Fudan Univ, State Key Lab ASIC & Syst, Shanghai 201203, Peoples R China 2.Chinese Acad Sci, Inst Modern Phys, Lanzhou 730000, Gansu, Peoples R China 3.Univ Chinese Acad Sci, Beijing 100049, Peoples R China
推荐引用方式 GB/T 7714	Xu, Liewei,Cai, Chang,Liu, Tianqi,et al. Design and verification of universal evaluation system for single event effect sensitivity measurement in very-large-scale integrated circuits[J]. IEICE ELECTRONICS EXPRESS,2019,16(10):6.
APA	Xu, Liewei,Cai, Chang,Liu, Tianqi,Ke, Lingyun,Yu, Jun,&Wu, Chang.(2019).Design and verification of universal evaluation system for single event effect sensitivity measurement in very-large-scale integrated circuits.IEICE ELECTRONICS EXPRESS,16(10),6.
MLA	Xu, Liewei,et al."Design and verification of universal evaluation system for single event effect sensitivity measurement in very-large-scale integrated circuits".IEICE ELECTRONICS EXPRESS 16.10(2019):6.