Efficient design of digital up converter for WCDMA in FPGA using system generator

doi:10.1109/ICIECS.2009.5366979

	Efficient design of digital up converter for WCDMA in FPGA using system generator
	Lin, Fei-Yu 1,2; Qiao, Wei-Ming 1; Jiao, Xi-Xiang1,2 ; Jing, Lan1 ; Ma, Yun-Hai1
	2009
会议地点	Wuhan, China
DOI	10.1109/ICIECS.2009.5366979
英文摘要	In this paper, we propose the design and implementation of the digital up converter (DUC) on xilinx FPGA for WCDMA. To shorten the design cycle and increase the design productivity, a powerful system design tool, Xilinx System Generator, is adopted. Submodules of the DUC, such as the RRC filter and the half-band filters, are designed using MATLAB FDATool and Xilinx FIR Compiler. The DDS submodule is produced by Xilinx DDS Compiler. Using Vitex-5 DSP48E slices, the complex multiplier operation frequency reaches 368.64MHz.The DUC needs to be pulse shaped and up sampled the baseband signal by a factor of 16 to 61.44MHz to meet the WCDMA specifications. Finally, we have implemented the DUC design on Xilinx XC5VSX50T FPGA device. ©2009 IEEE.
会议录	2009 International Conference on Information Engineering and Computer Science, ICIECS 2009
会议录出版者	IEEE Computer Society
内容类型	会议论文
源URL	[http://119.78.100.186/handle/113462/63946]
专题	中国科学院近代物理研究所
作者单位	1.Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou, China 2.Graduate School of the Chinese Academy of Sciences, Beijing, China
推荐引用方式 GB/T 7714	Lin, Fei-Yu,Qiao, Wei-Ming,Jiao, Xi-Xiang,et al. Efficient design of digital up converter for WCDMA in FPGA using system generator[C]. 见:. Wuhan, China.