A Parallel BP Neural Network Based on the FPGA

doi:10.4028/www.scientific.net/AMM.239-240.1541

	A Parallel BP Neural Network Based on the FPGA
	Qian Xiang-Ping 2; Guo Yu-Hui1 ; Zhou De-Tai1 ; Zeng Xian-Qiang 1; Yarlagadda, P ; Kim, YH
	2013
关键词	Neural network Field programmable gate array(FPGA) Back Propagation algorithm Parallel architecture System On Programmable Chip(SOPC)
卷号	239-240
DOI	10.4028/www.scientific.net/AMM.239-240.1541
页码	1541-+
英文摘要	This paper, with the analysis of BP neural network learning and execution algorithm on single computer unit, a parallel neural network on many computer units is constructed, a system on programmable chip based on FPGA and uClinux is provided. Because it's flexibility and reliability, this parallel neural network can be widely used where there is a large quantity of data to be processed. In addition to it, the system based on the SOPC has good versatility and easy to transplant because the reconfiguration of the hardware logic and software system.
会议录	MEASUREMENT TECHNOLOGY AND ITS APPLICATION, PTS 1 AND 2
会议录出版者	TRANS TECH PUBLICATIONS LTD
会议录出版地	KREUZSTRASSE 10, 8635 DURNTEN-ZURICH, SWITZERLAND
语种	英语
WOS研究方向	Automation & Control Systems ; Instruments & Instrumentation
WOS记录号	WOS:000317629800288
内容类型	会议论文
源URL	[http://119.78.100.186/handle/113462/58567]
专题	中国科学院近代物理研究所
通讯作者	Guo Yu-Hui
作者单位	1.Chinese Acad Sci, Inst Modern Phys, 509 Nanchang Rd, Lanzhou, Gansu, Peoples R China 2.Lanzhou Univ, Sch Nucl Sci & Technol, Lanzhou, Gansu, Peoples R China
推荐引用方式 GB/T 7714	Qian Xiang-Ping,Guo Yu-Hui,Zhou De-Tai,et al. A Parallel BP Neural Network Based on the FPGA[C]. 见:.