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	Design of FPGA Based Convolutional Neural Network Co-Processor
	Yang, Yichen; Zhang, Guohe; Liang, Feng; He, Ping; Wu, Bin; Gao, Zhenting
刊名	Hsi-An Chiao Tung Ta Hsueh/Journal of Xi'an Jiaotong University
	2018
卷号	52页码:153-159
关键词	Convolutional neural network General purpose processors Hardware acceleration Hardware parallelisms Internal communications Processing performance Programmable logic device Traditional industry
ISSN号	0253-987X
URL标识	查看原文
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/2830538
专题	西安交通大学
推荐引用方式 GB/T 7714	Yang, Yichen,Zhang, Guohe,Liang, Feng,et al. Design of FPGA Based Convolutional Neural Network Co-Processor[J]. Hsi-An Chiao Tung Ta Hsueh/Journal of Xi'an Jiaotong University,2018,52:153-159.
APA	Yang, Yichen,Zhang, Guohe,Liang, Feng,He, Ping,Wu, Bin,&Gao, Zhenting.(2018).Design of FPGA Based Convolutional Neural Network Co-Processor.Hsi-An Chiao Tung Ta Hsueh/Journal of Xi'an Jiaotong University,52,153-159.
MLA	Yang, Yichen,et al."Design of FPGA Based Convolutional Neural Network Co-Processor".Hsi-An Chiao Tung Ta Hsueh/Journal of Xi'an Jiaotong University 52(2018):153-159.

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