Constructing Sub-Arrays with Short Interconnects from Degradable VLSI   Arrays

doi:10.1109/TPDS.2013.114

CORC > 北京大学 > 软件与微电子学院

	Constructing Sub-Arrays with Short Interconnects from Degradable VLSI Arrays
	Wu Jigang ; Srikanthan, Thambipillai ; Jiang, Guiyuan ; Wang, Kai
刊名	ieee transactions on parallel and distributed systems
	2014
关键词	Reconfiguration degradable VLSI array fault tolerance routing algorithm FAULT-TOLERANT MESHES RECONFIGURATION SCHEME SELF-TEST EFFICIENT PROCESSORS SWITCHES DESIGNS
DOI	10.1109/TPDS.2013.114
英文摘要	Reducing the interconnection length of VLSI arrays leads to less capacitance, power dissipation and dynamic communication cost between the processing elements (PEs). This paper develops efficient algorithms for constructing tightly-coupled subarrays from the mesh-connected VLSI arrays with faulty PEs. For a given size tau.s of the target (logical) array, the proposed algorithm searches and reroutes a physical r x s subarray that has the least number of faults, resulting in an approximate target array, which is subsequently extended to the desired target array. Experimental results show that over 65 percent redundant interconnects can be reduced for a 64 x 64 target array on the 512 x 512 host array with no more than 1 percent faults. In addition, we propose a recursive divide-and-conquer algorithm for constructing the maximum target array (MTA). The lower bound of the total interconnection length of the MTA has been established. Experimental results show that the proposed algorithm is capable of reducing the long interconnects by over 33 percent for the MTA derived from the 512 x 512 host array with no more than 1 percent faults. Moreover, the proposed total interconnection length of target array is close to the lower bound for the cases with relatively fewer number of faults.; Computer Science, Theory & Methods; Engineering, Electrical & Electronic; SCI(E); EI; 2; ARTICLE; asjgwu@gmail.com; astsrikan@ntu.edu.sg; jguiyuan@gmail.com; morganwangk@hotmail.com; 4; 929-938; 25
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/214897]
专题	软件与微电子学院
推荐引用方式 GB/T 7714	Wu Jigang,Srikanthan, Thambipillai,Jiang, Guiyuan,et al. Constructing Sub-Arrays with Short Interconnects from Degradable VLSI Arrays[J]. ieee transactions on parallel and distributed systems,2014.
APA	Wu Jigang,Srikanthan, Thambipillai,Jiang, Guiyuan,&Wang, Kai.(2014).Constructing Sub-Arrays with Short Interconnects from Degradable VLSI Arrays.ieee transactions on parallel and distributed systems.
MLA	Wu Jigang,et al."Constructing Sub-Arrays with Short Interconnects from Degradable VLSI Arrays".ieee transactions on parallel and distributed systems (2014).