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	12-bits 50MHz Pipelined Low-Voltage ADC design
	Sun, Jinduo ; Cao, Xixin ; Cao, Jian ; Wu, Yadong ; Liu, Yue ; Zhang, Xing
	2008
英文摘要	In this paper, a 12-bit 50MHz Pipelined Low-Voltage ADC is presented, which consists of 8-stage-pipelined low resolution ADCs and a 4-bit flash ADC. Several critical technologies are used to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, gain-boosted telescopic OTA and so on. Finally the whole system is taped out in SMIC with its 0.13 um process successful, the test result testified all the specifications are well satisfied.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000258873500093&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Computer Science, Software Engineering; Engineering, Electrical & Electronic; Remote Sensing; Imaging Science & Photographic Technology; EI; CPCI-S(ISTP); 0
语种	英语
DOI标识	10.1109/CISP.2008.753
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/164182]
专题	软件与微电子学院
推荐引用方式 GB/T 7714	Sun, Jinduo,Cao, Xixin,Cao, Jian,et al. 12-bits 50MHz Pipelined Low-Voltage ADC design. 2008-01-01.

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