Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process

CORC > 北京大学 > 信息科学技术学院

	Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process
	Guangyi LU ; Yuan WANG ; Lizhong ZHANG ; Jian CAO ; Xing ZHANG
刊名	Science China(Information Sciences)
	2016
关键词	electrostatic discharge(ESD) power-rail ESD clamp circuit detection mechanism transient-noise immunity false triggering transmission line pulsing(TLP) test
英文摘要	This work presents the design of a novel static-triggered power-rail electrostatic discharge(ESD)clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit(TC), the proposed circuit achieves the best ESD-conduction behavior while consumin; 12; 170-178
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/479722]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Guangyi LU,Yuan WANG,Lizhong ZHANG,et al. Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process[J]. Science China(Information Sciences),2016.
APA	Guangyi LU,Yuan WANG,Lizhong ZHANG,Jian CAO,&Xing ZHANG.(2016).Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process.Science China(Information Sciences).
MLA	Guangyi LU,et al."Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process".Science China(Information Sciences) (2016).