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	Design Space Exploration of FPGA-based Accelerators with Multi-level Parallelism
	Zhong, Guanwen ; Prakash, Alok ; Wang, Siqi ; Liang, Yun ; Mitra, Tulika ; Niar, Smail
	2017
英文摘要	Applications containing compute-intensive kernels with nested loops can effectively leverage FPGAs to exploit fine-and coarse-grained parallelism. HLS tools used to translate these kernels from high-level languages (e.g., C/C++), however, are inefficient in exploiting multiple levels of parallelism automatically, thereby producing sub-optimal accelerators. Moreover, the large design space resulting from the various combinations of fine-and coarse-grained parallelism options makes exhaustive design space exploration prohibitively time-consuming with HLS tools. Hence, we propose a rapid estimation framework, MPSeeker, to evaluate performance/area metrics of various accelerator options for an application at an early design phase. Experimental results show that MPSeeker can rapidly (in minutes) explore the complex design space and accurately estimate performance/area of various design points to identify the near-optimal (95.7% performance of the optimal on average) combination of parallelism options.; Singapore Ministry of Education Academic Research Fund Tier 2 [MOE2015-T22-088]; CPCI-S(ISTP); 1141-1146
语种	英语
出处	20th Conference and Exhibition on Design, Automation and Test in Europe (DATE)
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/469862]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhong, Guanwen,Prakash, Alok,Wang, Siqi,et al. Design Space Exploration of FPGA-based Accelerators with Multi-level Parallelism. 2017-01-01.

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