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	Analytical Clustering score with application to post-placement multi-bit flip-flop merging
	Xu, Chang ; Li, Peixin ; Luo, Guojie ; Shi, Yiyu ; Jiang, Iris Hui-Ru
	2015
英文摘要	Circuit clustering is usually done through discrete optimizations, with the purpose of circuit size reduction or design-specific cluster formation. Specifically, we are interested in the multi-bit flip-flop (MBFF) design technique for clock power reduction, where all previous works rely on discrete clustering optimizations. For example, INTEGRA was the only existing post-placement MBFF clustering optimizer with a sub-quadratic time complexity. However, it degrades the wirelength severely, especially for realistic designs, which may cancel out the benefits of MBFF clustering. In this paper we enable the formulation of an analytical clustering score in nonlinear programming, where the wirelength objective can be seamlessly integrated. It has sub-quadratic time complexity, reduces the clock power by about 20% as the state-of-the-art techniques, and further reduces the wire-length by about 25%. In addition, the proposed method is promising to be integrated in an in-placement MBFF clustering solver and be applied in other problems which require formulating the clustering score in the objective function. ? Copyright 2015 ACM.; EI; 93-100; 29-March-2015
语种	英语
出处	18th ACM International Symposium on Physical Design, ISPD 2015
DOI标识	10.1145/2717764.2717767
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/449541]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Xu, Chang,Li, Peixin,Luo, Guojie,et al. Analytical Clustering score with application to post-placement multi-bit flip-flop merging. 2015-01-01.

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