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	Lin-Analyzer: A High-level Performance Analysis Tool for FPGA-based Accelerators
	Zhong, Guanwen ; Prakash, Alok ; Liang, Yun ; Mitra, Tulika ; Niar, Smail
	2016
英文摘要	The increasing complexity of FPGA-based accelerators, coupled with time-to-market pressure, makes high-level synthesis (HLS) an attractive solution to improve designer productivity by abstracting the programming effort above register-transfer level (RTL). HLS offers various architectural design options with different trade-offs via pragmas (loop unrolling, loop pipelining, array partitioning). However, non-negligible HLS runtime renders manual or automated HLS-based exhaustive architectural exploration practically infeasible. To address this challenge, we present Lin-Analyzer, a high-level accurate performance analysis tool that enables rapid design space exploration with various pragmas for FPGA-based accelerators without requiring RTL implementations.; EI; CPCI-S(ISTP); guanwen@comp.nus.edu.sg; alok.prakash@outlook.com; ericlyun@pku.edu.cn; tulika@comp.nus.edu.sg; smail.niar@univ-valenciennes.fr; 2016-August
语种	英语
出处	53rd ACM/EDAC/IEEE Design Automation Conference (DAC)
DOI标识	10.1145/2897937.2898040
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/449372]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhong, Guanwen,Prakash, Alok,Liang, Yun,et al. Lin-Analyzer: A High-level Performance Analysis Tool for FPGA-based Accelerators. 2016-01-01.

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