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	A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic
	Jia, Song ; Wang, Ziyi ; Li, Zijin ; Wang, Yuan
	2016
英文摘要	A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock (E-TSPC) scheme is presented. By restricting the short-circuit current in noncritical branchs, the design reduces the major source of power dissipation in E-TSPC scheme. The presented design enhances the maximum working frequency with shorter critical path and lower load capacitances. Simulation results in SMIC 40nm process show that compared with referenced E-TSPC based designs at least 61.2% (divide-by-2) and 41.1% (divide-by-3) reduction in power delay product (PDP) can be achieved by the proposed design. ? 2016 IEEE.; EI; 2751-2754; 2016-July
语种	英语
出处	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
DOI标识	10.1109/ISCAS.2016.7539162
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/449343]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Jia, Song,Wang, Ziyi,Li, Zijin,et al. A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic. 2016-01-01.

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